Legality of type conversion on instance ports?

Yes. There was a change from VHDL-87 to VHDL-93 that fixed a silly inconsistency: VHDL-87 didn't accept array type conversions on a port map, so for example if you have a std_logic_vector signal S and you want to connect it to an "unsigned" input port P:

... port map (... P => unsigned(S) ...)

is legal in VHDL-93 but was forbidden in '87.

Mostly, yes.

The workaround is hardly a big deal, though. Just tedious. It may be cleaner to do the workaround by building a wrapper entity, so that you can hide the type conversion and its associated extra signal in the wrapper rather than exposing it in the upper-level entity.

Actually, this syntax was ok: port map (... P => unsigned(S) ...)

While this was not: port map (... unsigned(A) => B ...)

I don't understand why they haven't fixed this... Is there any sort of option to toggle VHDL-93 syntax? I can't find any mention of it in the XST user guide...

If you don't mind, could you explain the wrapper workaround? I made the changes manually myself, but that involved creating a duplicate signal to perform the type conversion on. This is quite sloppy imo, and I dislike having to tailor my code to a specific tool.

Thanks a bunch.

ok - both versions should be absolutely fine, assuming A is an output port of course. Both forms were made legal in VHDL-93 (in VHDL-87 it would have been necessary to write your own function, something like "my_unsigned", so that the conversion is a function call rather than an array type conversion)

Not enough people shouting about it, I guess.

You must have VHDL-93 enabled already, otherwise the input-port conversion would also have been illegal.

Well... the code you end up with will work in any tool OK, it's just that it is tiresome to do. I wasn't suggesting anything different - just another layer of module instantiation so that the conversion is not visible in the top-level module:

entity Original is port (P: in unsigned(...); Q: out std_logic_vector(...)); end;

entity Wrapper is port (P: in std_logic_vector(...); Q: out unsigned(...)); end; architecture Hack of Wrapper is signal QU: unsigned(...); begin Original_Instance: entity work.Original(arch) port map (P => unsigned(P), Q => QU); Q

Actually I did use functions to perform the conversion. For some reason it only complained when the function call was on the left hand side of the port map.

Thanks for the help.