Hello, I know this is a off-the-wall question, but bear with me. In my effort to become more efficient and improve my design process in my FPGA design I always create a top block diagram that is either a Block Design File (.bdf) or a Graphic Design File (.gdf). If you are not familiar with these files, they are basically a schematic where you can graphically add symbols and connect symbols via wires or buses. I believe using these files reduces complexity, and creates documentation while you design. I know it does take some time placing the wires, which is why some don't uses these files in their fpga design. In addition, using these graphical files allows you to create a hierarchical design which again helps manage complexity and makes the design easier to modify/maintain. I'm just wondering how many people use some sort of graphic design in their FPGA programs? I see so many benefits of doing so, but my co-workers see it as a waste of time placing those wires and symbols they would just rather have a design contain lots of .vhdl, .v, and .tdf files. Any thoughts, comments, suggestions, experiences on the topic? I'm not trying to be picky, its just when I see a tool that can help reduce complexity if can't understand why people wouldn't use it.