Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

partial reconfig with multipiers

hi there, i am trying to generate a partial bitstream for a module using a multipier. the code is quite simple, just a...
0 comments posted 21yrs
posted by eem
0 comments posted 21yrs posted by eem

What are IO standard defaults in S3 ?

If you don't specify IO standards, drive etc. in the UCF for a Spartan3, what default settings are used ?
2 comments posted 21yrs
posted by mike
2 comments posted 21yrs posted by mike

START /STOP sync pattern

Hi all, I am implementing some logic in FPGA(Transmit/Reveive). On the receive data first i look for a 8- bit pattern t...
3 comments posted 21yrs
posted by praveen.kantharajapura
3 comments posted 21yrs posted by praveen.kantharajapura

Incorporating Cores to the Virtex2Pro PLB

Does anyone possess an example of a core incorporated to the PLB of Virtex2Pro especially if the design is using FIFOs....
3 comments posted 21yrs
posted by nrivera.eng
3 comments posted 21yrs posted by nrivera.eng

how to reduce vga memory????????

hi.. i m using spartan-2 ......... and have designed a very simpl vga controller on it ...... now i wanna interface an...
10 comments posted 21yrs
posted by fahadislam2002
10 comments posted 21yrs posted by fahadislam2002

can use bram for VGA

hi.......... in sparton-2 ......for disply(VGA) controller ...i wann use bram...........can??????how????????
8 comments posted 21yrs
posted by fahadislam2002
8 comments posted 21yrs posted by fahadislam2002

warning for ODDR primitive?

Hey, i get this warning from the bitgen log and i was wondering if this is a problem or just a warning i can ignore? WA...
1 comments posted 21yrs
posted by tim.verstraete
1 comments posted 21yrs posted by tim.verstraete

ZLIB anyone?

Anyone worked on a ZLIB implementation? I am solely interested in the RLC only version. Cheers, Irish
0 comments posted 21yrs
posted by decalternate
0 comments posted 21yrs posted by decalternate

sequence detection using shift register approach

Hi, I want to design a sequence detector circuit, there are two approaches . The first approach is the traditional stat...
4 comments posted 21yrs
posted by praveen.kantharajapura
4 comments posted 21yrs posted by praveen.kantharajapura

Hiding data inside a FPGA

Hello, I am working on cryptographic application over VirtexII FPGAs. I need to store a simmetric key inside a reg of t...
11 comments posted 21yrs
posted by jcastillo
11 comments posted 21yrs posted by jcastillo

ModelSim Error

hi could somebody help me with this error message i get from model sim se? i'm trying to simulate (post place and route...
1 comments posted 21yrs
posted by u_stadler
1 comments posted 21yrs posted by u_stadler