Field-Programmable Gate Arrays

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Linux on Viretex-II pro

Hi, I just got a board with a Viretex-II pro FPGA. I'm a newbie and have several questions that would like to get some...
1 comments posted 21yrs
posted by dasani8888
1 comments posted 21yrs posted by dasani8888

Cyclone conf flash - 25p10 !

Hi, I've been using the 25P10 flash to configure cyclone devices, as far as I can see they are exactly equal to the EPC...
19 comments posted 21yrs
posted by cupidoREMOVE
19 comments posted 21yrs posted by cupidoREMOVE

Any GOSPL Docs?

Hi All, Despite the demise of the GOSPL project, I'm wondering if there are any documents available from when the proje...
0 comments posted 21yrs
posted by ajg112
0 comments posted 21yrs posted by ajg112

ANN: Altera Power Net Seminar #2

Hi, On Thursday (Sept 6) Sanjay Rajput and I will be giving a Net Seminar entitled "Comparing Stratix II & Virtex-4 Pow...
2 comments posted 21yrs
posted by paulleventis-news
2 comments posted 21yrs posted by paulleventis-news

SI newsgroup

Does anyone here know of any Signal Integrity Newsgroups?
1 comments posted 21yrs
posted by blah
1 comments posted 21yrs posted by blah

Partial vector range in instance warning

Hi, I am getting ready to clean up some XST(Verilog) warnings, and want to open a discussion on how to eliminate/suppre...
1 comments posted 21yrs
posted by newman5382
1 comments posted 21yrs posted by newman5382

Spartan 3E and Spartan 3 with GTL

Hello I'm wondering what alternatives I have to GTL on an Spartan 3E. I would like to use an output pin as an open coll...
0 comments posted 21yrs
posted by nosmap
0 comments posted 21yrs posted by nosmap

PCI on ML310 Xilinx board

Hello, I'm trying to use Linux 2.6 on the ML310 Xilinx board with PCI support. After adding the PCI bridge, I generate...
4 comments posted 21yrs
posted by sgowal
4 comments posted 21yrs posted by sgowal

SPARATAN 2E - input clock

Is it possiable to arrive clock signal to spartan 2e, if I have already used all global clocks (device compromises 4 gl...
1 comments posted 21yrs
posted by sinebrate
1 comments posted 21yrs posted by sinebrate

Disconnect the FPGA I/O pads from the outside world

Hello all, What is the method to isolate a FPGA (XCV600E) from a bus. I am asking this because i observed starnge behav...
5 comments posted 21yrs
posted by vssumesh_asic
5 comments posted 21yrs posted by vssumesh_asic

Carry saver adder

Does anyone know the use of block "*2" (multiplication by 2) in a carry saver adder?
0 comments posted 21yrs
posted by mehul_sun
0 comments posted 21yrs posted by mehul_sun