Latest threads in Field-Programmable Gate Arrays

spartan 3 starter kit auto configuration at power up

hi how do we program the spartan 3 starter kit to load the configuration from PROM automatically at start up. Thank you....

2 20yrs

manusha

2 20yrs manusha

WARNING:HDLParsers:3481 - No primary, secondary unit in the file

I have been using CoreGen to generate the DCMs on a Spartan3 project. After going through the wizzard, I can select the...

0 20yrs

bradsmallridge

0 20yrs bradsmallridge

Cyclone conf flash - 25p10 !

Hi, I've been using the 25P10 flash to configure cyclone devices, as far as I can see they are exactly equal to the EPC...

19 20yrs

cupidoREMOVE

19 20yrs cupidoREMOVE

Any GOSPL Docs?

Hi All, Despite the demise of the GOSPL project, I'm wondering if there are any documents available from when the proje...

0 20yrs

ajg112

0 20yrs ajg112

ANN: Altera Power Net Seminar #2

Hi, On Thursday (Sept 6) Sanjay Rajput and I will be giving a Net Seminar entitled "Comparing Stratix II & Virtex-4 Pow...

2 20yrs

paulleventis-news

2 20yrs paulleventis-news

SI newsgroup

Does anyone here know of any Signal Integrity Newsgroups?

1 20yrs

blah

1 20yrs blah

Final Call for Participants CPA 2005 (18-21 Sept 2005) in Eindhoven

Hi, (Sorry if you received this more than once; for some reason I didn't see it appear on the news servers I have poste...

0 20yrs

herman7

0 20yrs herman7

Partial vector range in instance warning

Hi, I am getting ready to clean up some XST(Verilog) warnings, and want to open a discussion on how to eliminate/suppre...

1 20yrs

newman5382

1 20yrs newman5382

Spartan 3E and Spartan 3 with GTL

Hello I'm wondering what alternatives I have to GTL on an Spartan 3E. I would like to use an output pin as an open coll...

0 20yrs

nosmap

0 20yrs nosmap

PCI on ML310 Xilinx board

Hello, I'm trying to use Linux 2.6 on the ML310 Xilinx board with PCI support. After adding the PCI bridge, I generate...

4 20yrs

sgowal

4 20yrs sgowal

SPARATAN 2E - input clock

Is it possiable to arrive clock signal to spartan 2e, if I have already used all global clocks (device compromises 4 gl...

1 20yrs

sinebrate

1 20yrs sinebrate

Disconnect the FPGA I/O pads from the outside world

Hello all, What is the method to isolate a FPGA (XCV600E) from a bus. I am asking this because i observed starnge behav...

5 20yrs

vssumesh_asic

5 20yrs vssumesh_asic

Carry saver adder

Does anyone know the use of block "*2" (multiplication by 2) in a carry saver adder?

0 20yrs

mehul_sun

0 20yrs mehul_sun

Quartus2 WEB: Simulating from test bench. Is that possible?

Hello: Quartus 2 Web edition has a build in Modelsim simulator, which seems to work, but: But I can only (so far) simul...

2 20yrs

no

2 20yrs no

Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed."

Hello All, I am facing a very bugging problem while using XILINX ISE 7.1i with SP4 installed. Some of my top level port...

2 20yrs

vijayandra.poojari

2 20yrs vijayandra.poojari

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