Hey,
I made a FSM with about 23 states (not the first time i've done vhdl work, but never had this problem before with FSM => in fact it is not really a problem) and i used following scheme:
sequencing:process(state,...) begin case state is when ... =>
end case; end process;
update:process(reset, clk) begin if (reset='1') then state
oh, and i forgot to mention that it found the FSM in ISE6.1 but not in ISE7.1 ...
the result:
Found finite state machine for signal .
----------------------------------------------------------------------- | States | 23 | | Transitions | 82 | | Inputs | 38 | | Outputs | 28 | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset State | idle_st | | Power Up State | idle_st | | Encoding | automatic | | Implementation | LUT |
-----------------------------------------------------------------------
...
Perhaps XST is expecting a one or two process format.
But as you said, this is not really a problem if sims and runs as you expect. A few dubious statistics are not worth much extra work.
-- Mike Treseler
What fitter is used ?
I had a similar problem (which is not solved yet) with Synplify. I used the following attributes as workaround:
SIGNAL ls_ddr_state, next_ls_ddr_state : ddr_state_type; attribute syn_keep : boolean; attribute syn_keep of ls_ddr_state : signal is true; attribute nomerge : boolean; attribute nomerge of ls_ddr_state : signal is true;
Rgds Andr=E9
Mike Treseler schrieb:
What fitter is used ?
I had a similar problem (which is not solved yet) with Synplify. I used the following attributes as workaround:
SIGNAL ls_ddr_state, next_ls_ddr_state : ddr_state_type; attribute syn_keep : boolean; attribute syn_keep of ls_ddr_state : signal is true; attribute nomerge : boolean; attribute nomerge of ls_ddr_state : signal is true;
Rgds Andr=E9
Mike Treseler schrieb:
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