• posted

Hi I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how to define a signed number? I've the following situation:

reg [7..0] p1 //(is an unsigned value from AD converter) 0..255 reg [7..0] p2 // is the unsigned value that we should have 0..255

now I want to substract p1-p2, to have the differenz, to correct the error reg[7..0] diff //should be a signed value

how do I define this in Verilog HDL

best regards remo

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• posted

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Signed and unsigned addition are the same. Their results is to be interpreted differently though ...

Let's says the number are 4 bits unsigned :

1001 = 9 0100 = 4 -------- 01101 = 13

now if they are 4 signed : 1001 = -7 0100 = 4

---------

01101 = -3

See, the method to do the computation is the same but what it _means_ is different ...

Now, you want to substract 2 unsigned number of seven bits so the result to avoid overflow should be 9 bits. I don't know verilog but in vhdl that would give

diff

• posted

almost right

01101 /= -3 11101 = -3

you need to sign extend ;-)

Sim> > Hi

how

error

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• posted

Damn, my bad ... typed quicker than I thought ;)

• posted

wire signed [9:0] op1;

assign op1 = subtract_u11[9:0]; assign add_u3 = 12'sh7E1 + multiply_u3_b_signed;

0x7E1 is a signed constant by definition of the 's

news.green.ch wrote:

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• posted

Surely not for the example given. The fifth bit there was the carry bit from a 4 bit operation. Thus the answer only takes 4 bits and is correct. The carry bit is used for error detection. If the carry into the MSB and the carry out of it are different, the 2's complement operation has overflowed. The overflow bit in a processor is just the result of an exclusive or on the two carries.

Pete Harrison

Sylvain's original sums:

• posted

depends.. try entering 01101 into VHDL and see what you get :-) you are either exact or error. true or false 1 or 0 this is binary logic..

1101 maybe -3 .. but 01101 isn't

Simon

from

overflowed.

the

• posted

In Verilog, I do it by defining all variables as signed. Then it's automatic.

reg [7:0] p1; reg [7:0] p2 wire signed [8:0] p1s; wire signed [8:0] p2s; wire signed [8:0] diff;

assign p1s = p1; assign p2s = p2; assign diff = p1s - p2s;

Notice that I made all variables 9-bits to ensure that values up to

255 will be treated as positive numbers and so that the result can represent the full range of -255 to +255.

Marko

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• posted

you could make them all signed... but have you ever looked at symplify's output? if you use a signed 8 bit number for a counter counting from 0 to

255, then it will generate a 'warning count is not used' I personally check every warning and every error... I've had designs producing several hundred warnings ... all of which are just junk (code portability). but try to get it down to less than 20 warnings by the time the project is finished. so I will stick to signed types.. and unsigned types... unsigned by default as unsigned math is easier and signed only when absolutely necessary

Simon

how

error

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