Field-Programmable Gate Arrays

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Xilinx IPIF PLB Master Update

Hello All: Jsut an update on my efforts on using the Xilinx IPIF for a PLB master. Per another user's recommendation (t...
1 comments posted 21yrs
posted by emh203
1 comments posted 21yrs posted by emh203

How many decoupling capacitors need on one device?

Hi, all. I'm newbie in circuits, and I have a silly question. Suppose that one FPGA device has about 100 Vcc pins (incl...
5 comments posted 21yrs
posted by river064
5 comments posted 21yrs posted by river064

Questions on DCI split termination of spartan-3

Hi, everyone. I want to use bank 4 and bank 5 of Xilinx spartan device XC3S1500-4fg676 for LVDS_25 interface. I have fo...
0 comments posted 21yrs
posted by codejk
0 comments posted 21yrs posted by codejk

Clock routing

Hi, I have routed an input clock from an input pin directecly to an output pin and I used this clock (too) to all my de...
1 comments posted 21yrs
posted by patrick.melet
1 comments posted 21yrs posted by patrick.melet

systemc to verilog translator v0.5

Hello, We have released the version 0.5 of the SystemC to Verilog Synthesizable Subset Translator, wich includes suppor...
0 comments posted 21yrs
posted by jcastillo
0 comments posted 21yrs posted by jcastillo

VHDL : Use concatenation on port mapping

Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM:...
6 comments posted 21yrs
posted by me00569
6 comments posted 21yrs posted by me00569

Yet another NGDBUILD 455 problem

Good day, I'm sorry to start another thread on the notorious NGDBUILD 455 problem while using Xilinx ISE, however I sim...
0 comments posted 21yrs
posted by merlin_jiang
0 comments posted 21yrs posted by merlin_jiang

Vector, Signal and Image Processing Library

Is anyone here doing anything to do with VSIPL? I've been working on a VSIPL project for a few months now, looking at d...
0 comments posted 21yrs
posted by robin.bruce
0 comments posted 21yrs posted by robin.bruce

16550 VHDL code

Hello, I'm currently writing VHDL code for an Altera cyclone, the EP1C6. One of the modules i need is an 16550 compatib...
1 comments posted 21yrs
posted by Jackolantern25
1 comments posted 21yrs posted by Jackolantern25

Bus master DMA and cache coherency

Hello, Hopefully these groups are appropriate for this quesiton, apologies if not. I've designed a PCI card that does d...
0 comments posted 21yrs
posted by gfriend-nospam
0 comments posted 21yrs posted by gfriend-nospam

Library Simprim cannot be found?

hello! When I use ths XST to synthesis(Simulate Post-translate VHDL Modele) a project,it tells me errors: ERROR:HDLPars...
0 comments posted 21yrs
posted by seabrench
0 comments posted 21yrs posted by seabrench

3rd party JTAG cables/controllers for Virtex-4

I think I know that answer all ready, but I just wanted to but out the question... Is there any 3rd party JTAG cable/con...
4 comments posted 21yrs
posted by chris
4 comments posted 21yrs posted by chris

Opal help please

Hello all I am sure this is a trivial question for you all,but i am getting tired of breaking pins off my gal lol. How...
0 comments posted 21yrs
posted by fpbankroll
0 comments posted 21yrs posted by fpbankroll

New Ethernet Development board, open-source

Hiya all, I just put out my new Dev. board that's open source, but I do sell assembled units. Thought I would just the...
0 comments posted 21yrs
posted by jai.dhar
0 comments posted 21yrs posted by jai.dhar

PowerPC interrupt latency

Hello Has anyone here had experience with interrupt latency in a PowerPC block in a VirtexII Pro? I did a simple experi...
1 comments posted 21yrs
posted by emh203
1 comments posted 21yrs posted by emh203