Field-Programmable Gate Arrays

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Doubt in using CD22M3494

Hi, We are using CD22M3494(16 X 8 audio switch).Which has 128 switches. Now initially i connect switch X0 to switch Y0...
1 comments posted 20yrs
posted by praveen.kantharajapura
1 comments posted 20yrs posted by praveen.kantharajapura

24 to 32 8-bit PWM outputs

I have an application where I need to implement 24 or up to 32 PWM outputs (8-bit) and am considering using a small CPL...
9 comments posted 20yrs
posted by noaddress
9 comments posted 20yrs posted by noaddress

SoC Processor design at gate level for edu

Hi Folks, For educational purpose (Von Neumann demo), I am looking for a System On Chip Processor : - very simple - gat...
6 comments posted 20yrs
posted by raphael.ponsard
6 comments posted 20yrs posted by raphael.ponsard

RS232 Uart for Virtex-II Pro

Does anyone know if there's a ready-to-use rs232 uart in vhdl for the Virtex-II pro fpga? We have done some designs in I...
3 comments posted 20yrs
posted by dasani8888
3 comments posted 20yrs posted by dasani8888

FPGA Design Docs

I work in a large company. Two years ago, most of our FPGA developments were over budget and schedule. Management wante...
3 comments posted 20yrs
posted by no
3 comments posted 20yrs posted by no

write on a DG834GT modem

Hi all, I'm looking for proper tools to write on a DG834GT modem. I've been using debricks soft, but for some reason I...
0 comments posted 20yrs
posted by aldus.toon
0 comments posted 20yrs posted by aldus.toon

clock frequency after RTL synthesis vs PAR

dear all I have a question on how to get maximum clock frequency of real hardware. i am using XST and ISE6.3 Cnsider fo...
4 comments posted 20yrs
posted by pasacco
4 comments posted 20yrs posted by pasacco

.dat to .bit

Hi all, I have this xess board which has a tool to initialise an SDRAM with data. I have 16-bit numbers that I want to...
3 comments posted 20yrs
posted by subhasri.krishnan
3 comments posted 20yrs posted by subhasri.krishnan

Internal Loading in Spartan3

I am using the EDK to configure a sytem using the MicroBlaze core. We have several user IP's that are used to perform v...
0 comments posted 20yrs
posted by tlassiter
0 comments posted 20yrs posted by tlassiter

Coregen Memory Initialization (.coe file format)

Hi, I am trying to use Coregen to generate a single port memory with its content initialized. I defined a memory with d...
0 comments posted 20yrs
posted by robertsolanki
0 comments posted 20yrs posted by robertsolanki

RISC pipelining question

Hi, Do you guys know the difference between the following two instructions: LW 0(R1), F2 LW F2, 0(R1) Are they equivale...
0 comments posted 20yrs
posted by bobrics
0 comments posted 20yrs posted by bobrics

netgen port renaming

hi, how i can prevent netgen (ise7.1i) from renaming std_logic_vector ports like this X1_CON(7 downto 0) -> X1_CON_0_Q,...
0 comments posted 20yrs
posted by wassatsch
0 comments posted 20yrs posted by wassatsch

ML401

I would like to buy an ML401 Board from Xilinx. Would somebody give me some indications about this card? Does it have a...
2 comments posted 20yrs
posted by taileb.mehdi
2 comments posted 20yrs posted by taileb.mehdi

low power design and unused i/os

I believe that connecting any unused i/os to gnd instead of leaving them floating helps in static power dissipation in...
6 comments posted 20yrs
posted by fpgabuilder-news
6 comments posted 20yrs posted by fpgabuilder-news

"Cannot synthesize logic..." ERROR

Hi, I am trying to synthesize hardware which changes one values in a register array at rising and falling edge of the c...
6 comments posted 20yrs
posted by bobrics
6 comments posted 20yrs posted by bobrics