Xilinx FIFO Generator: FIFO Length

You "chose an asynchronous FIFO" design. Why? Is your design synchronous, with the same clock for read and write? If so, use the synchronous design, it is much simpler and easier to understand. What is the max clock rate? Which Virtex or Spartan family? Peter Alfke

I chose the asynchronous one because I need two different clocks for reading and writing. Clock for write is 128 MHz. clock for read is 32 MHz.

VirtexII, VP50.

This is not an answer to your query but rather a question to you:

How did you include the generated FIFO from Core Generator in your project? (I am assuming you're using ISE)

Did you have to compile the cores seperately? Or did ISE take care of it?

If your 32 MHz clock is really derived from, and thus synchronous with, the 128 MHz, then I would treat this as a synchronous FIFO. Asynchronous means that you have no idea of, and no control over, the phase relationship between the two clocks. And asynchronous FIFO control is far trickier than synchronous, just because of the unknown and shifting phase relationships, and the associated possible decoding glitches and even metastability. Synchronism makes all this so much easier. Peter Alfke

I use ISE7.1. FIFO Generator works exactly like other cores. I just clicked on "Add new Source...". When I used ISE6.3 I was not able to get FIFO Generator work, it always generated empty cores!

In the final design they should be synchronous, I should get them from a DCM with a 64MHz input. Now I just create them in the testbench. Anyway I don't think this is the problem, the test I'm performing is very simple, first I raise the wr_enable, I wait for the FULL signal, and then I lower the wr_enable and after a little bit of time I raise the rd_enable.

I understand that asynchronous FIFOs are more trickier than synchronous ones ... but I don't want to use a synchronous FIFO, the clocks relation is not fixed, their ratio could change in the future. So I'm just asking, is possible to store 16 words in a 16 words deep FIFO? Or "Deep N" means that I can only store N-1 words? Is this problem somehow related to the old asynchronous-fifo core behaviour? I remember that it let me chose only the length like

Nemesis ha scritto:

OK, I just read carefully the summary screens that appears at the of the FIFO customization ... When you chose an asynchronous FIFO it says: "Write Depth:15 Read Depth:15. Actual FIFO depth differs from specified depth in this configuration". So this is a "limit" of the asyncrhonous FIFO.

It's possible, but not simple. Keeping track of 0 to 16 words in a FIFO requires 17 states. That won't fit in 4 bits.

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OK. Is this true also for synchronous FIFO? In this case FIFO Generator announce a depth equal to 16