Hi,
I am new in VLSI field. I have written one verilog code to calulate evenparity of two input data.
EX: input data1 input data2 output eparity output overflow output code
whenevr either data1 or data2 are with evenparity increment eparity, if eparity reaches FF , increment overflow. if data1 = AA or data2 = 55 increment code.
following is code which i have written , i just want to know is this efficient code, or i can still improve code.
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module assg (clock,clear,reset, datain1, datain2, evenparity,overflow,greycode);
input clock; input reset; input clear; input [7:0] datain1; input [7:0] datain2;
output [7:0] evenparity; output overflow; output [7:0] greycode; reg [7:0] evenparity; reg overflow; reg [7:0] greycode; always @(posedge clock or negedge reset)
begin if(!reset) begin evenparity=0; overflow=0; greycode=0; end else begin if(clear) begin evenparity = 0; greycode = 0; overflow = 0; end else begin if(~^datain1) evenparity= evenparity + 1; if(~^datain2) evenparity= evenparity + 1; if(evenparity==8'b11111111) overflow = overflow + 1; if(datain1==8'b10101010) greycode = greycode + 1; if(datain2==8'b01010101) greycode = greycode + 1; end end
end
endmodule
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if anyone can suggest any improvement in design