Field-Programmable Gate Arrays

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consensus theorem and power

I am wondering if it is possible to reduce switching activity in the next state logic if I use consensus theorem (term)...
3 comments posted 20yrs
posted by fpgabuilder-news
3 comments posted 20yrs posted by fpgabuilder-news

Xst Error

Hi, I was trying to implement my design in Xilinx ISE using Xst as the Synthesis tool. It gave me a error INTERNAL_ERRO...
1 comments posted 20yrs
posted by rxv20
1 comments posted 20yrs posted by rxv20

Error in MAP (Xlinx Project navigator)

Hi All, when I synthesize my design in xilinx project navigator, I get an error message, "ERROR:MapLib:681 - LOC constr...
0 comments posted 20yrs
posted by shanthalr
0 comments posted 20yrs posted by shanthalr

Custom data rates with Virtex 2 Pro-X MGTs

Has anyone had any experience using Xilinx RocketIO MGTs at data rates other than the PMA rates that are explicitly def...
0 comments posted 20yrs
posted by jjcannon
0 comments posted 20yrs posted by jjcannon

Incremental Compilation in Quartus 5.1?

Hi, I was wondering if anyone could comment on using Incremental Compilation in Quartus 5.1? Is there any problems parti...
1 comments posted 20yrs
posted by jjlindula
1 comments posted 20yrs posted by jjlindula

FPGA-pci communication

I have a virtex II pro fpga pci board. I have to transfer data from fpga to the host computer over the pci bus.How shou...
9 comments posted 20yrs
posted by nitesh.guinde
9 comments posted 20yrs posted by nitesh.guinde

Mission critical & low core voltages

Hi We're looking at using an FPGA in a land based mission critical application (not life critical). The latest generati...
8 comments posted 20yrs
posted by dave.bryan
8 comments posted 20yrs posted by dave.bryan

Simulating CRC32 according to IEEE Std. 802.3

Hi, I have been googling for a while having noticed that there is no clear answer to my following problem: The IEEE Std...
6 comments posted 20yrs
posted by ALuPin
6 comments posted 20yrs posted by ALuPin

Can ISE 4.2 program Virtex 2 6000K devices?

Just got the old PC from the storage of the lab which has ISE 4.2 installed. I only need the PC to program Virtex 6000 a...
2 comments posted 20yrs
posted by Francis.invalid
2 comments posted 20yrs posted by Francis.invalid

J Tag Protocol

hi all has anyone got any documents or refferals for 'J Tag Protocol ' , for reconfigurable hardware. i would appreciate...
5 comments posted 20yrs
posted by abhishekbedi
5 comments posted 20yrs posted by abhishekbedi

ISE WebPack 8.1i

Hi all! Does anybody knows why the Xilinx ISE Foundation 8.1i is already released but not the ISE WebPack 8.1i ? Mehdi
7 comments posted 20yrs
posted by taileb.mehdi
7 comments posted 20yrs posted by taileb.mehdi

SGMII Interface

Not quite on topic - but I thought somebody here might know - Does anybody know where I can get hold of the SGMII spec...
2 comments posted 20yrs
posted by jeremy
2 comments posted 20yrs posted by jeremy

Frequency dependent SOPC builder components

Hello all, I'm designing a component for integration in Altera's SOPC builder, for which I have to set some frequency d...
3 comments posted 20yrs
posted by avishorp
3 comments posted 20yrs posted by avishorp

Future of Microchip Development Tools?

http://Microcontroller.com/Embedded.asp?did=142 I'm taking a fast short survey of Microchip users to help decide what f...
4 comments posted 20yrs
posted by editor
4 comments posted 20yrs posted by editor

fiddling directly with LUT bits on Xilinx

Hi All Is there anyway to directly stash bits into Xilinx (Spartan in this case) LUTs ? I need to hand-build a very smal...
3 comments posted 20yrs
posted by jdc-rootbeer
3 comments posted 20yrs posted by jdc-rootbeer