Hi,
I have been googling for a while having noticed that there is no clear answer to my following problem:
The IEEE Std. 802.3 says the following: (section 3.2.8 Frame Check Sequence field)
Mathematically,the CRC value corresponding to a given frame is de =EF=AC=
=81ned by the following procedure:
a)The =EF=AC=81rst 32 bits of the frame are complemented.
>=2E..
>e)The bit sequence is complemented and the result is the CRC.
I use the following CRC32-VHDL module:
-- File: PCK_CRC32_D8.vhd
-- Purpose: VHDL package containing a synthesizable CRC function
-- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- * data width: 8
-- Info: snipped-for-privacy@easics.be
Now I want to simulate the CRC according to the IEEE standard. I have a transmitter including the CRC32 module and a receiver including the CRC32 module. But I have some doubts on how to perform a conform simulation.
Let's assume that the following bytes are transmitted via Ethernet(one byte interface), they are fed into the easics- module: byte0 =3D "00000000" (Integer 0) byte1 =3D "00000001" (Integer 1) .=2E. byte255=3D"11111111" (Integer 255)
Are the following assumptions correct ?
1=2E The CRC has to be initialized to NOT ("00000011 00000010 00000001 00000000")
2=2E The calculated CRC has to be inverted and appended in the following manner: first byte appendix: NOT CRC(31 DOWNTO 24) second byte appendix NOT CRC(23 DOWNTO 16) third byte appendix NOT CRC(15 DOWNTO 8) fourth byte appendix NOT CRC(7 DOWNTO 0)
3=2E To which value do I have to reset the "remote" CRC module ?
4=2E Do I have to remove the CRC32 appendix of the Ethernet packets and replace the four bytes with "00000000" ?
I would be very thankful if you could shed some light on it.
Rgds Andr=C3=A9