I was wondering if anybody had designed a vhdl sram controller for the Digilent Memory Expansion board that is designed for the spartan 3 starter kit. It is just two ISSI IS61LV5128AL sram chips. I have tried writing a controller but cant seem to get it to work!!
fpga-cpu group threads about async SRAM strobe & OE timing:
fpga-cpu post with S3 kit SRAM tester:
The archive for that is here ftp://members.aol.com/fpgastuff/ram_test.zip
And a post on re-compiling it under 7.1 :
That example includes pipelined SRAM control logic (registered address, data, and tristate contols in IOB registers, gated write pulse ) for the Xilinx/Digilent S3 eval kit.
I've started a newer version of that, using a DCM duty cycle tweak, that works at around 60 Mhz with address & data lines all in SLOW slew rate mode, I'll probably update that archive file sometime next month.