I was wondering if anybody had designed a vhdl sram controller for the Digilent Memory Expansion board that is designed for the spartan 3 starter kit. It is just two ISSI IS61LV5128AL sram chips. I have tried writing a controller but cant seem to get it to work!!
Thanks, I'm not using EDK, only ISE, so I need a simple controller for the CE, OE and WE pins and to put the data and address on the correct buses at the right times.
"al99999" schrieb im Newsbeitrag news: snipped-for-privacy@g49g2000cwa.googlegroups.com...
that is just plain wires, if you have some circuitry that the SRAM can be connected.
if you have trouble then just use VIO in chipscope, connected the SRAM to VIO pins and check the that the sram is really working properly, then go ahead and check your desing
fpga-cpu group threads about async SRAM strobe & OE timing:
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fpga-cpu post with S3 kit SRAM tester:
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The archive for that is here ftp://members.aol.com/fpgastuff/ram_test.zip
And a post on re-compiling it under 7.1 :
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That example includes pipelined SRAM control logic (registered address, data, and tristate contols in IOB registers, gated write pulse ) for the Xilinx/Digilent S3 eval kit.
I've started a newer version of that, using a DCM duty cycle tweak, that works at around 60 Mhz with address & data lines all in SLOW slew rate mode, I'll probably update that archive file sometime next month.
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