Digilent SRAM Controller

"al99999" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

SRAM doesnt need an controller, just connect it to whatever you want, if you did it right and the hardware is ok it will work.

for EDK just add an EMC IP core to the SoC and setup the port connection in the ucf file, thats should be it.

Antti

Thanks, I'm not using EDK, only ISE, so I need a simple controller for the CE, OE and WE pins and to put the data and address on the correct buses at the right times.

"al99999" schrieb im Newsbeitrag news: snipped-for-privacy@g49g2000cwa.googlegroups.com...

that is just plain wires, if you have some circuitry that the SRAM can be connected.

if you have trouble then just use VIO in chipscope, connected the SRAM to VIO pins and check the that the sram is really working properly, then go ahead and check your desing

Antti

Here is a RAM tester for the S3 kit:

It'll probably help you.

Leon

Thanks, trying to use VIO in chipscope with the code below and getting the following error:

ERROR:Xst:2091 Different types for port on entity and component for .

Any ideas?

Thanks

entity vio_top is Port( control: in std_logic_vector(35 downto 0); async_in: in std_logic_vector(7 downto 0) ); end vio_top;

architecture structure of vio_top is

------------------------------------------------------------------- -- -- VIO core component declaration -- ------------------------------------------------------------------- component vio port ( control : in std_logic_vector(35 downto 0); async_in : in std_logic_vector(7 downto 0) ); end component;

begin

------------------------------------------------------------------- -- -- VIO core instance -- ------------------------------------------------------------------- i_vio : vio port map ( control => control, async_in => async_in );

end structure;

fpga-cpu group threads about async SRAM strobe & OE timing:

fpga-cpu post with S3 kit SRAM tester:

The archive for that is here ftp://members.aol.com/fpgastuff/ram_test.zip

And a post on re-compiling it under 7.1 :

That example includes pipelined SRAM control logic (registered address, data, and tristate contols in IOB registers, gated write pulse ) for the Xilinx/Digilent S3 eval kit.

I've started a newer version of that, using a DCM duty cycle tweak, that works at around 60 Mhz with address & data lines all in SLOW slew rate mode, I'll probably update that archive file sometime next month.

Brian