Field-Programmable Gate Arrays

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[ANNOUNCE] MyHDL 0.5 released

Hi all: I'm pleased to announce the release of MyHDL 0.5. MyHDL is an open-source package for using Python as a hardwar...
4 comments posted 20yrs
posted by jan
4 comments posted 20yrs posted by jan

DCM and buffers

hi I have another question about DCM's: If I use the design wizard to generate a vhdl file for a DCM the wizard uses al...
1 comments posted 20yrs
posted by u_stadler
1 comments posted 20yrs posted by u_stadler

Using posedge and negedge causing me grief

First off, let me point out that I'm a newbie trying to teach myself verilog. :) I get warnings (shown below) whenever...
10 comments posted 20yrs
posted by oxlargeMike
10 comments posted 20yrs posted by oxlargeMike

Xilinx upgrade issues

OK, assume I'm a helpless manager droid and take pity on me. We have some old Xilinx designs that were done under Found...
8 comments posted 20yrs
posted by jjlarkin
8 comments posted 20yrs posted by jjlarkin

XST error Xst:2035

hi thanks for the answers on my last post. unfortunatly i stumbled across another problem: has anybody seen this error:...
2 comments posted 20yrs
posted by u_stadler
2 comments posted 20yrs posted by u_stadler

Coding style

Hi, Does anyone happen to know what will the following (software) code will look like after going through a synthesis t...
3 comments posted 20yrs
posted by <khtsoi
3 comments posted 20yrs posted by <khtsoi

My design to big for the FPGA or not?

When I try to generate a programming file for my FPGA project I get the following error: ERROR:Place:419 - The design c...
2 comments posted 20yrs
posted by casio
2 comments posted 20yrs posted by casio

Clock generation

hi I have a question: what is the proper way to generate c slow clock. I have a spartan 3 development board with a 50 M...
16 comments posted 20yrs
posted by u_stadler
16 comments posted 20yrs posted by u_stadler

What is the best solution vor PCIe today ?

Hello, We'll have to design a new board which will have a PCIe interface. There will be a xilinx FPGA V2P or V4 because...
4 comments posted 20yrs
posted by t
4 comments posted 20yrs posted by t

optimization tips (badly) needed

hello friends, For better security, I am porting a design from Xilinx (Spartan3) to Actel (ProAsic3E). The Actel part i...
7 comments posted 20yrs
posted by burn.sir
7 comments posted 20yrs posted by burn.sir

Problem in Serial Port Transmitter

Hi, This code is not working for me (nothing is shown in hyperterm). Could someone tell me any possible errors? //-----...
1 comments posted 20yrs
posted by singhal.prateek
1 comments posted 20yrs posted by singhal.prateek

fx12

XC4VFX12-10SF363CES is 157$ and XC4VFX12-10FF668CES is 189$ at Avnet. When will be available these devices for full pro...
2 comments posted 20yrs
posted by yusufilker
2 comments posted 20yrs posted by yusufilker