Latest threads in Field-Programmable Gate Arrays

FPGA DVI output with CH7301

Hi does anybody have some experience with DVI output using Chrontel DVI transmitter (CH7301) the DVI transmitter works...

14 20yrs

antti

14 20yrs antti

Start up condition of flip flops in FPGA?

Hello Must I always include an reset signal to force all used flip flops to a zero condition? If I write an entity that...

7 20yrs

bill

7 20yrs bill

Ethernet Multiplexers

Hello All,, I need to implement Ethernet Multiplexer in FPGA. I need to draft the requirement specifications also. Can...

0 20yrs

kedarpapte

0 20yrs kedarpapte

FPGA running diff with simulation

Hi all: I download my design(A 5 pipeline CPU) to FPGA(Altera Stratix), But it runs diff with what I expected. Some sig...

3 20yrs

luiguo

3 20yrs luiguo

Microbalze program initialization ...

Hi all, I'm currently working on a FPGA design including a microbalze (as a sub-system). When simulating my design ever...

2 20yrs

Moti.cohen

2 20yrs Moti.cohen

basic DSP with FPGA

Hi all, I'm new to FPGA stuff... i have an idea of making an audio spectrum analyzer implemented on a fpga, displaying...

17 20yrs

drgenio

17 20yrs drgenio

Why 'a plurality of N' must be used for 'N' in patent claims

Hi, Why 'a plurality of N' or 'the plurality of N' must be used fo 'N' in patent claims? What is the difference between...

11 20yrs

wtxwtx

11 20yrs wtxwtx

Timing problem in ModelSim, Post-Route Simulation.

Hi, I'm doing a Post-Route Simulation simulation in ModelSim V6.1a and having problem with physical paths delays. The p...

9 20yrs

ndf

9 20yrs ndf

Low cost PCI FPGA cards for reconfigurable computing

What are the recomendations for low end PCI FPGA cards with at least 15,000 LUTs?

2 20yrs

air_bits

2 20yrs air_bits

Fitting circuits to fpga LUTs

The FpgaC internal algorithm is pretty generic, and just decideds pretty early on to force all internal functions to 4-...

1 20yrs

air_bits

1 20yrs air_bits

open source xnf to edif script

Does anybody know of an open source xnf to edif converter we can use with FpgaC? A C program would be fine, as would a...

0 20yrs

air_bits

0 20yrs air_bits

Free ASIC & EDA/ISD Magazines

1993 through 2002 last issue. Call to arrange pick-up in Redwood City, California. Gary, 650-568-9333.

0 20yrs

gembler

0 20yrs gembler

Newbie question - using library "design elements"

I've got the Spartan-3 starter board, and in going through the ISE 7.1i documentation I see that there are "design elem...

3 20yrs

oxlargeMike

3 20yrs oxlargeMike

Easy and fun: Worlds smallest FPGA module.

A picture says more then words but having something on your hands is even better. I found lately that an German company...

4 20yrs

antti

4 20yrs antti

How do I instantiate an ADSU8 in ISE7.1i?

Hi, I am trying to use the ADSU8 library element in ISE7.1i. The libraries guide says its inferred by HDL (Verilog in m...

1 20yrs

pm940

1 20yrs pm940

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays