[ANNOUNCE] MyHDL 0.5 released

Looks impressive, and interesting.

Do you have any Simulation benchmark indications, and any simple, example 'complete' side-by-side projects ? By simple, I mean things like 16/24/32 bit Up/Dn/ReLoad counter, perhaps a DDS as well, and since it seems to have good ROM/RAM support, a 7 segment display counter ?

-jg

Simulation performance is basically limited by the Python interpreter. Compared to mainstream HDL simulators, I expect a performance degradation similar to Python versus C. Therefore, raw simulation performance is not a good argument in favor of MyHDL at this point. Fortunately, there are many other good reasons :-)

No, but it seems like a good idea to set up such a page on the web site. Perhaps you have a pointer to Verilog/VHDL code for such relevant designs?

Jan

You might be surprised, which was why I was curious. There are functional simulation, and timing simulation tasks,

- you might not be as slow as you think, on the functional areas, where higher levels can help.

I'll see what I can find, and email some to you. Such simple examples are not as common as they should be, on vendors web sites.

-jg

For those interested, I have started a "MyHDL Cookbook", with a first example: