Hi,
This code is not working for me (nothing is shown in hyperterm). Could someone tell me any possible errors?
//------------------------------------------------- // RS-232 TX module // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005
//`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations) //`define RegisterInput // in RegisterInput mode, the input doesn't have to stay valid while the character is been transmitted
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy); input clk, TxD_start; input [7:0] TxD_data; output TxD, TxD_busy;
parameter ClkFrequency = 25000000; // 25MHz parameter Baud = 115200;
// Baud generator parameter BaudGeneratorAccWidth = 16; reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc; `ifdef DEBUG wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h10000; `else wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud5))/(ClkFrequency>>4); `endif
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth]; wire TxD_busy; always @(posedge clk) if(TxD_busy) BaudGeneratorAcc