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Using posedge and negedge causing me grief

First off, let me point out that I'm a newbie trying to teach myself verilog. :)

I get warnings (shown below) whenever I try to assign values to a register in a "always @ (posedge clk)" block, and change the values in a "always @ (negedge clk)" block.

My thinking is that I want to update an internal register on the negedge, and then present it to the output on the posedge. I'm pretty sure that my thinking is wrong because if I "`ifdef" out the negedge block the warning goes away. [The logic also stops working, but that's not the point.]

As a final note, this logic simulates just fine.

Thanks for looking at this for me. I appreciate the help.

-MO

module top(clk, reset, enable, cnt);

input clk,reset,enable; output cnt;

wire clk,reset,enable; reg [3:0] cnt, curval, ov1; reg [1:0] acnt;

always @ (posedge clk) begin if (reset) begin curval

Reply to
Mike Oxlarge
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-snip-

I would guess that you're working with a chip that only supports clocking on one edge of any given clock line. If you want to implement a two-phase clock you'll probably have to do it explicitly.

On recent Xilinx parts it looks like you can do this more or less directly with a DCM or a DLL -- figuring out how is up to you.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Reply to
Tim Wescott

Thanks for the speedy reply.

I'm working with the XS3S200 Spartan 3 device, on a Spartan-3 starter board. I'll have to do some digging in the docs to see if what you've suggested is true for my device. Thanks again.

Reply to
Mike Oxlarge

To be frank I don't think your issue is whether your chip supports mixed edge clocks etc but basic logic design background. To do regular digital logic you don't need mixed edges as you describe above. The flops already do that for you internally. You need to partition your design into combinational blocks and storage and you use the flop as a storage element which samples its input every clock edge and presents it to the output. Your combinational blocks also depend on the current value of the storage but as you need an edge for it to be sampled the loop is cut at the input of the flop so to speak. You don't need a two phase implementation which necessiates mixed clock edges. You can do everything you need with a single edge. Imagine a cloud of logic which takes your enable and the cnt value and calculates the next value of cnt to be presented. When the clock edge happens this value gets to the flop output and the cycle starts again. No need for an internal phase. HTH.

Reply to
m

There's Verilog and there's synthesizeable Verilog.

Not everything you can write in Verilog turns into sensible hardware.

The basic rules for syntheizeable code are that only a single block can drive a register unless tristates/multiplexors are used. You update curval on both edges.

Perhaps the curval reset logic should be done on the negedge ?

Jon

Reply to
Jon Schneider

crurval is reset in the posedge block, and assigned in the negedge block. Move the reset to the negedge block, and it should work.

Andy

Reply to
Andy

Reply to
Andy Peters

I get what you're saying, and have tried your (and the other's) suggestion of putting the reset in the negedge-clocked block, and it synthesizes just fine. However, I'm now trying to implement what mk suggested:

... You don't need a two phase implementation which necessiates mixed clock edges. You can do everything you need with a single edge. Imagine a cloud of logic which takes your enable and the cnt value and calculates the next value of cnt to be presented. When the clock edge happens this value gets to the flop output and the cycle starts again. ...

Any ideas on how I can implement what he suggested? I'm working on it, but not making much progress. I'm sure there's probably a simple and elegant solution to this that I'm missing.

Reply to
Mike Oxlarge

My suggestion would be eliminate using both the posedge and negedge conditions in your design and just use posedge for the clock edge.

You have created a half-cycle path in your design when it appears that you have no need to do so. This will likely lead to a race condition (aka hold violation) where some of the data gets through the other edge when it shouldn't have or a setup violation where the data doesn't get to the register on the other edge in time.

Unless you really need to use opposite edges for a very specific timing reason you should avoid doing so it minimize lengthy debug sessions where the design works when it's cold and then starts to fail when it warms up or the reverse.

Ed

Reply to
Ed McGettigan

To be frank I am not sure what your code is trying to do but let me start it here and you can fix it the way you want:

always @ (posedge clk) begin if (reset) begin curval

Reply to
mk

Thanks for setting me straight with not using a mixed phase approach. I had only used it because I had seen it used as an example somewhere on the internet. It was probably either a bad example, or I just didn't get the point of the code. I do see the need to keep to a single clk edge, and to use a combinational block (or combinational plus sequential) to calculate my next value.

Many thanks to you, and everyone else who offered guidance and advice.

-MO

Reply to
Mike Oxlarge

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