My design to big for the FPGA or not?

You can make the design fit.

Change your BlockRAMs to use x18 width instead of x36. The multipliers can share the resources with a BlockRAM unless the BlockRAM uses the wide 36-bit bus. Since you're only using 4 BlockRAMs, it would be easy from a resource perspective to use half of 8 BlockRAMs at 18-bit width to give you the same memory sizes you have now. You may be able to reoptimize for 18-bit width and use just 4 of the BlockRAM and avoid the troubles altogether.

Another thought might be to access the BlockRAMs at twice the base clock speed to provide 36-bit operation over 2 18-bit cycles making it look to the system like it's a 36-bit BlockRAM at the normal clock rate. This approach is more complex but often the BlockRAMs aren't pushed to their maximum speed and time-multiplexing produces cleaner resource usage.

Casio wrote:

Thank you very much, it solved my problem. I had a RAM entity that was 50 bits wide and a total of 64 words. Now I split the 50-bit words into 18, 18 and 14 bits.

Thanks :-)

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