Hello all,
I am monica from germany.I am using xilinx spartan 3 FPGA.I have a peculiar problem with DCM in spartan 3 FPGA.
The input frequency to the FPGA is from another system which gives a frequency arround 40 MHz and the FPGA is supposed to generate 1/8 th of the input frequency,I have implemented it by using DCM.dcmLocked is asserted(dcm locked) and it works fine.
On certain conditions the input frequency changes from 40 MHz to
60MHz,now dcmLocked is still asserted(shows that dcm locked) but the output divided clock's duty cycle is not 50% it is varying spuriously which is really annoying.i think DCM still thinks that it is having 40MHz input signal and tries to lock to it,but it is giving dcmLocked as '1' which is wrong.Either it should give dcmLocked as '0' or give the correct clock output,but it is giving wrong clock output as well as wrong dcmLocked signal.
Can anybody give me an idea how to solve this frequency division problem?
I will be obliged if anyone can give me a hint/pointers to solve this problem.
Thank you very much Monica Dsouza, Germany