VHDL FF Question

Hi All,

I am new to VHDL and am attempting to create an object similar to a parallel load register. Each FF loads its input from the same signal and all are clocked by the same signal. In my "entity" definition I desire only the two inputs as I don't want to use any more IOB's. In the architecture block I declare a signal that is an N-bit vector (say N=8). However Xilinx ISE 7.1 seems to optimize out the F/F's becuase they are logically not required. Here is the question; how does one declare a set of F/F's to be instantiated in "slices" not "IOB's" whose outputs are not used (to be manually routed later)?



Reply to
Brendan Illingworth
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Didnt understand clearly what you are trying to do.Can you post your entity and architecture to throw some light on it?

Cheers, Monica, Germany

Reply to

You can attach an attribute to the signal, (in the architecture part of the VHDL code) that tells the tools not to optimise it away. Depending on the synthesis tool you are using, the attribute can have value "no_opt" or "keep" or "preserve_signal". Check the tool documentation for details.

- Brian

Reply to
Brian Drummond

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