I am new to VHDL and am attempting to create an object similar to a parallel load register. Each FF loads its input from the same signal and all are clocked by the same signal. In my "entity" definition I desire only the two inputs as I don't want to use any more IOB's. In the architecture block I declare a signal that is an N-bit vector (say N=8). However Xilinx ISE 7.1 seems to optimize out the F/F's becuase they are logically not required. Here is the question; how does one declare a set of F/F's to be instantiated in "slices" not "IOB's" whose outputs are not used (to be manually routed later)?