A problem of the Dynamic Partial Reconfiguration

Hi All: I have project of the Reconfiguration.I saw the paper "A Module-Based Dynamic Partial Reconfiguration" and maked the same project. In my project(it is a up / down counter), I had a addition partial bitstream (up counter)and a subtraction(down counter) bitstream and a top routed bitstream. When I loaded up partial bitstream with FPGA,the counter could work correct , but when the partial bitream loaded up FPGA the counter was halt.

Someone can tell me what's wrong with it?

I used xc2s200 ,ISE 6.2i

Alan Chen

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