URGENT: Virtex-II Pro X - Clock correction questions

In my design I use the block sync and the 64B/66B descrambler and bypasses the 64B/66B decoder in the Rx direction of the MGT.

In the Tx direction I bypass the 64B/66B encoding and applies the sync header in the fabric i/f. I use the gearbox and the scrambler.

I want to use the Rx buffer clock correction function and I have defined a 66-bits pattern used for this purpose as follows: 0x01_5555000000000000

My problem is to get a correct match of the pattern. In my simulation the pattern is matched independent of the sync header, i.e. both 01 and

10 matches. I have configured the MGT as follows:

CLK_COR_SEQ_1_1 = "11001010101" CLK_COR_SEQ_1_2 = "10001010101" CLK_COR_SEQ_1_3 = "10000000000" CLK_COR_SEQ_1_4 = "10000000000" CLK_COR_SEQ_1_MASK = "0000" CLK_COR_SEQ_2_1 = "10000000000" CLK_COR_SEQ_2_2 = "10000000000" CLK_COR_SEQ_2_3 = "10000000000" CLK_COR_SEQ_2_4 = "10000000000" CLK_COR_SEQ_2_MASK = "0000" CLK_CORRECT_USE = true CLK_COR_MAX_LAT = 48 -- According to UG035 v1.5 table 1-5 CLK_COR_MIN_LAT = 32 -- According to UG035 v1.5 table 1-5 CLK_COR_SEQ_2_USE = false

I have also tried to use the opposite syncheader value for my sequence (10) but it still fails.

Is it possible to say which serial bits that are matched with which bits of the generics/attributes debending of the diffrent configurations? It should be some kind of mux that connects the bits to the comparator logic.

Looking forward for Your answers.

Best Regards Patrik Eriksson

------ Patrik Eriksson

Reply to
Patrik Eriksson
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Hi Patrik,

I'm sorry I cannot offer any advice on your question, however I can tell you that marking a request as "URGENT" is the surest way to have it ignored.

As the old saying goes, "A lack of planning on your part does not constitute an emergency on mine.". A potential footnote to that is, "(unless you're paying)".

Regards,

John

Patrik Erikss> In my design I use the block sync and the 64B/66B descrambler and

Reply to
John Williams

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