ISE Timing

Hi Rob,

Unfortunately I cannot help answer your question, but felt I should respond because I am interested in knowing the answer to the "clock skew" question as well. I have been attempting to find an answer using the Xilinx Timing Analyzer, with no answer so far. Have you had any luck?

Best, Brendan

No, I haven't. I know how to do it with Quartus (frankly, I think they do a better overall job with timing constraints). All I want to do is get the fanout timing from an output of a DCM--why is so difficult?

Try placing a PERIOD constraint on the DCM output in which you are interested -- the precise time value isn't important. The timing analyzer will report on that constraint and hopefully show you what you want to see. You may need to use the "-v nnn" verbose reporting option (where nnn is the number of items to report) in the fanout is very large and you want to see everything.

Here's a link to some Xilinx documentation that may or may not help --

Cheers,

Russ