I have an EDK project with a bunch of Xilinx cores and a bunch of custom cores. All the custom cores are attached to the OPB. I am using Synplify for the synthesis of all cores, save for the microblaze.
The results of synthesis are output as an edn EDIF file. For some of the cores I am getting an EDIF file that has the USER_LOGIC_I (instantiated in the top-level vhdl wrapper) referenced as....
(instance USER_LOGIC_I (viewRef netlist (cellRef user_logic_32s_4s (libraryRef dependency_lib)))
So for this one, the USER_LOGIC_I is a netlist.
Some give this:
(instance USER_LOGIC_I (viewRef syn_black_box (cellRef user_logic_work_tx_data_control_wrapper_structure_0))
So for this one, the USER_LOGIC_I is a black_box
Why does synplify give two different synthesis results for essentially the same thing? These are both USER_LOGIC_I cores. They both do very different things, but why would one be a netlist and the other a black box? The black box cores cause errors when run through NGDBuild at a top-level (intantiated from system.edn).
Hope this makes sense. It is more of a Synplify question.