I can't figure out how to use alias to create vectors of arbitary signals...
What I want to do is this (Using ISE 6)
signal lcdbufadr:std_logic_vector(10 downto 0); alias lcdbufburst:std_logic_vector(2 downto 0) is lcdbufadr(1) & lcdbufadr(0) & lcdbufadr(8);
but the compiler is complaining - what is the correct syntax, or can't it be done ?
It can be done, but I don't do it because alias identifiers are not visible in simulation. If the expression is used more than once, declare and assign a variable or signal. ... is variable lcdbufburst_v : std_logic_vector(2 downto 0); begin lcdbufburst_v := lcdbufadr(1) & lcdbufadr(0) & lcdbufadr(8); ...
-- Mike Treseler
What you're trying to do is an expression with operators (&) that requires execution. This cannot be aliased. An alias must be of all, or a contiguous part, of an existing object, with no execution required.
You could alias to a slice of an array, but not to a concatenation of bits in an array.
Otherwise, what Mike said.
Andy
I realise that & is probably not the right operator..
All I want do do is alias a group of bits that are not consecutive in the original signal, so I can assign values to them as a group in a fashion that is logical for my application, instead of assinging to each bit seperately.
If I can make an alias of bits 3,2 and 1 of a vector signal, why can't I do the same thing with bits, say, 8, 4 and 2 instead? All I want to do is the same thing where the bits are not consecutive - There is no execution required.
Seems a bizarre limitation if this is not possible but then again the more I use VHDL the more I'm surprised at how primitive and unfriendly it is in some respects...!
Andy is correct. I can't use any operator as an alias. An alias is just an alternate name for a slice of an existing variable or signal. Your example is more than a simple rename.
use VHDL the more I'm
It's not the only one. VHDL started as a simulation language. There are many language features like alias, block, wait, etc that seem like they ought to be useful for synthesis, but just aren't.
-- Mike Treseler
ps: David Bishop said it best: "VHDL was written by a bunch of software guys who knew nothing about designing hardware. We beat on it until you could do hardware with it. Verilog was written by a bunch of hardware guys who knew nothing about designing software. We beat on it until you could do software with it. Neither does the job they were originally intended to do, but they work."
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