Instead of using INIT_XX=>"...." I would like to write like "INIT(W,A)=>D" where W is the buswidth and D is the initial value (including parity bus) at the port at adress A. This is a plain mapping function and maybe someone has done this before me so I dont have to rewrite it?
You still need the init_xx= attributes , however you can put the primitive inside a wrapper and write a set of functions to deconstruct an integer array passed as a generic and generate the proper init_xx attributes. You can even handle data split across multiple BRAMs this way.
Do it with a vhdl function (I am assuming you are using VHDL, this would be really ugly with verilog) that accepts the data array (array of integers, passed into your wrapper as a generic), an index which corresponds to the XX in INIT_XX, and the msb and lsb of the slice the function is to generate. From the widht of the field (msb:lsb) you can infer the length of the output bit vector, as well as the address into your integer array that holds the data. The output of the function is a bit vector to match the generic on the BRAM primitive. You can write a second function to convert the bit vector to the hex string needed for the attribute.
Doh.. I missed on the parity bits. You need to flip INITP00 lines so that MSB (init3F(35 downto 32) appears first.. same for the other INITP0x's. Too fast copy and paste.. :p
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