Field-Programmable Gate Arrays

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Xilinx Virtex-4 BRAM-16 Simulation

Does anyone have a Virtex-4 BRAM16 simulation running? I have been trying for two days now to get a simulation to work...
13 comments posted 20yrs
posted by bradsmallridge
13 comments posted 20yrs posted by bradsmallridge

Xilinx ISE 8.i Editor

I use to be able to write over text by pressing the Insert key. What has changed? Is there another way to write over?
3 comments posted 20yrs
posted by bradsmallridge
3 comments posted 20yrs posted by bradsmallridge

Directed routing in Xilinx V2PRO.

All, I've got some directed routing constraints in my UCF file. After some recent changes I get the following message i...
7 comments posted 20yrs
posted by symon_brewer
7 comments posted 20yrs posted by symon_brewer

WebPack 8.1 report viewing

In version 6.1 of the XIlinx tools, I was able to configure the s/w to use an external editor (in my case, gvim) to vie...
0 comments posted 20yrs
posted by johnp3+nospam
0 comments posted 20yrs posted by johnp3+nospam

bandpass filter design for ACTEL FPGA

Anyone have experience with designing band pass filters for ACTEL FPGAs? Tools, appnotes anything is of interest. I my...
1 comments posted 20yrs
posted by mughat
1 comments posted 20yrs posted by mughat

PCI e clocking

Hello, I don't have the specification of PCI e ( that doesn't help ! ) and I'm trying to figure out how the clock schem...
8 comments posted 20yrs
posted by t
8 comments posted 20yrs posted by t

Xilinx 8.i and ML402

I just downloaded the 8.i Webpack and it won't program the ML402 SX35 :(
2 comments posted 20yrs
posted by bradsmallridge
2 comments posted 20yrs posted by bradsmallridge

OT: RoHS and Lead?

Excuse the OT post, but I figured people in this group may have an answer for this odd question: In transitioning to Ro...
37 comments posted 20yrs
posted by 0_0_0_0_
37 comments posted 20yrs posted by 0_0_0_0_

FPGA Journal Article

I'm writing a feature article for FPGA Journal (www.fpgajournal.com) about FPGAs and the re-birth of the electronics ho...
107 comments posted 20yrs
posted by kevin
107 comments posted 20yrs posted by kevin

boundary scan of altera epm570F

Guys I'm going home with a problem unsolved. After an ALTERA EPM570F has been programmed can it still be boundary scann...
3 comments posted 20yrs
posted by colin_toogood
3 comments posted 20yrs posted by colin_toogood

Xilinx simullation error

After switching from ISE 6.i to 7.i (What is the i anyway? integer?) I find that I can simulate a dcm ok but can't simu...
0 comments posted 20yrs
posted by bradsmallridge
0 comments posted 20yrs posted by bradsmallridge

Xilinx Vertex II Pro with tow VDEC videodevices

Hello, I want to use a second Digilent VDEC videodevice at one time with another on the Vertex II Pro Developmentsystem...
1 comments posted 20yrs
posted by Ludwig.Lenz
1 comments posted 20yrs posted by Ludwig.Lenz

Newbe Startup Time Question

Hi, I'm completely new to FPGA:s. Assume the FPGA is up and running and all startup settings are initiated. How long do...
3 comments posted 20yrs
posted by dannymarcus
3 comments posted 20yrs posted by dannymarcus

How to create a delay BUF?

Hi,in my project,i need some bufs to delay some signals,but after synthesising,the code:#20 does't have any affects.Is...
10 comments posted 20yrs
posted by wuyi316904
10 comments posted 20yrs posted by wuyi316904

Conflicts between ISE4.2 and win2000 SP4

Hi,I have a problem that i can't use ISE4.2 download design in CPLD or FPGA with win2000 SP4 system.The iMPACT of ISE4....
6 comments posted 20yrs
posted by wuyi316904
6 comments posted 20yrs posted by wuyi316904