Latest threads in Field-Programmable Gate Arrays

custom ip using EDK

Hi, I designed a simple adder using the add/import peripheral feature in EDK. I removed the sum register in the write p...

4 20yrs

dasani8888

4 20yrs dasani8888

How to handle the "gate count" issue?

Hi all, I need some advice on how to treat the "equivalent gate count" issue. I have to make a presentation on somethin...

5 20yrs

tirath

5 20yrs tirath

testbench.tdo file Xilinx ISE 7.1

I've run into a weird error. I've been successfully calling Modelsim from the ISE gui for the functional sim for weeks....

0 20yrs

cwoodring

0 20yrs cwoodring

undefined reference to `xilkernel_main'

I am usig xilkernel on microblaze spartan 3 board. I am getting an unusua error that is undefined reference to `xilkern...

1 20yrs

akhammad

1 20yrs akhammad

Verilog tutorial by John Sanguinetti

Hi, I'm looking for a functional URL that hosts the Verilog tutorial by John Sanguinetti. Neither of these seem to work...

4 20yrs

eric.crabill

4 20yrs eric.crabill

Newbie: xilinx vs arm

Hello, My knowledge on fpga field is almost zero. Ive got few questions. I would like to enter into fpga world. Ive tho...

4 20yrs

unlogic

4 20yrs unlogic

rocket IOs with web pack

Guys Does anyone know whether ISE simulator lite will simulate the RocketIOs on the virtex 4 that webpack supports? I h...

1 20yrs

colin_toogood

1 20yrs colin_toogood

problem to synthetize with ISE

Hello, I get trouble to run a project(synthetize and p&r) It complete sucessfully all the steps but it doesn't validate...

2 20yrs

KCLO4[no_spam]

2 20yrs KCLO4[no_spam]

help:dual-edge flip-flop possible using Verilog?

Im designing a module working as an fm0-encoder, the clk and max datarate of which are both 640KHz. It is not complicat...

26 20yrs

yyqonline

26 20yrs yyqonline

LVDS Input buffer in VHDL (ISE)

I'm trying to instantiate some LVDS input buffers in VHDL using the following code: LVDS_lines: for i in 0 to 19 genera...

9 20yrs

enquiries

9 20yrs enquiries

obtaining ABEL code from schematics sou rce in a design with ISE Webpack ¿?

i'm testing webpack8.1, with a CPLD. i would like to create a design from an schematic and obtain as a result the equiv...

1 20yrs

fperalQUITAESTO

1 20yrs fperalQUITAESTO

FPGA board with High Speed LVDS

Hi, I am looking for a board with at least 16 balanced LVDS connections able to run at 800 MHz, preferably A but X woul...

2 20yrs

kal*

2 20yrs kal*

Virtex-4 BiDirectional Ports

How does one properly synthesize and simulate a bidirectional port on the Virtex-4 using ISE 7.1i. I drafted code from...

1 20yrs

bradsmallridge

1 20yrs bradsmallridge

Xilinx ISE & StateCad

Good morning, I've designed with statecad a state machine and tested with statebhench all seems to be OK, now I want to...

1 20yrs

etantonio

1 20yrs etantonio

RPM.

Hi Guys, I've got an V2PRO RPM that uses only FFs in slices. How do I prevent ISE7.1 from placing the RPM so that it st...

2 20yrs

symon_brewer

2 20yrs symon_brewer

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