Field-Programmable Gate Arrays

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How to handle the "gate count" issue?

Hi all, I need some advice on how to treat the "equivalent gate count" issue. I have to make a presentation on somethin...
5 comments posted 20yrs
posted by tirath
5 comments posted 20yrs posted by tirath

testbench.tdo file Xilinx ISE 7.1

I've run into a weird error. I've been successfully calling Modelsim from the ISE gui for the functional sim for weeks....
0 comments posted 20yrs
posted by cwoodring
0 comments posted 20yrs posted by cwoodring

undefined reference to `xilkernel_main'

I am usig xilkernel on microblaze spartan 3 board. I am getting an unusua error that is undefined reference to `xilkern...
1 comments posted 20yrs
posted by akhammad
1 comments posted 20yrs posted by akhammad

Verilog tutorial by John Sanguinetti

Hi, I'm looking for a functional URL that hosts the Verilog tutorial by John Sanguinetti. Neither of these seem to work...
4 comments posted 20yrs
posted by eric.crabill
4 comments posted 20yrs posted by eric.crabill

Newbie: xilinx vs arm

Hello, My knowledge on fpga field is almost zero. Ive got few questions. I would like to enter into fpga world. Ive tho...
4 comments posted 20yrs
posted by unlogic
4 comments posted 20yrs posted by unlogic

rocket IOs with web pack

Guys Does anyone know whether ISE simulator lite will simulate the RocketIOs on the virtex 4 that webpack supports? I h...
1 comments posted 20yrs
posted by colin_toogood
1 comments posted 20yrs posted by colin_toogood

problem to synthetize with ISE

Hello, I get trouble to run a project(synthetize and p&r) It complete sucessfully all the steps but it doesn't validate...
2 comments posted 20yrs
posted by KCLO4[no_spam]
2 comments posted 20yrs posted by KCLO4[no_spam]

help:dual-edge flip-flop possible using Verilog?

Im designing a module working as an fm0-encoder, the clk and max datarate of which are both 640KHz. It is not complicat...
26 comments posted 20yrs
posted by yyqonline
26 comments posted 20yrs posted by yyqonline

LVDS Input buffer in VHDL (ISE)

I'm trying to instantiate some LVDS input buffers in VHDL using the following code: LVDS_lines: for i in 0 to 19 genera...
9 comments posted 20yrs
posted by enquiries
9 comments posted 20yrs posted by enquiries

FPGA board with High Speed LVDS

Hi, I am looking for a board with at least 16 balanced LVDS connections able to run at 800 MHz, preferably A but X woul...
2 comments posted 20yrs
posted by kal*
2 comments posted 20yrs posted by kal*

Virtex-4 BiDirectional Ports

How does one properly synthesize and simulate a bidirectional port on the Virtex-4 using ISE 7.1i. I drafted code from...
1 comments posted 20yrs
posted by bradsmallridge
1 comments posted 20yrs posted by bradsmallridge

Xilinx ISE & StateCad

Good morning, I've designed with statecad a state machine and tested with statebhench all seems to be OK, now I want to...
1 comments posted 20yrs
posted by etantonio
1 comments posted 20yrs posted by etantonio

RPM.

Hi Guys, I've got an V2PRO RPM that uses only FFs in slices. How do I prevent ISE7.1 from placing the RPM so that it st...
2 comments posted 20yrs
posted by symon_brewer
2 comments posted 20yrs posted by symon_brewer

Configuration Spartan 3

Hi We work with a XCF01S and a Spartan 3 XC3S200. JTAG works with 2.5V, Spartan Vcco (INIT_B and DIN/D0) has 3.3V. The...
5 comments posted 20yrs
posted by luigi.zadra
5 comments posted 20yrs posted by luigi.zadra