Field-Programmable Gate Arrays

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Configuration Spartan 3

Hi We work with a XCF01S and a Spartan 3 XC3S200. JTAG works with 2.5V, Spartan Vcco (INIT_B and DIN/D0) has 3.3V. The...
5 comments posted 20yrs
posted by luigi.zadra
5 comments posted 20yrs posted by luigi.zadra

SSOs and Vcco on Spartan3

Hi, on xapp623 on PDS there are all the step to define the number and the values of decoupling capacitors. This number...
6 comments posted 20yrs
posted by marco
6 comments posted 20yrs posted by marco

Reconfigurable Array of Array

just for fun I wrote down how I see it possible to have different FPGAs to be cut out from single wafer covered with co...
5 comments posted 20yrs
posted by antti
5 comments posted 20yrs posted by antti

Webpack 8.1i size

I have been evaluating this lately... and I see from the install that Xilinx still isn't acting very friendly on intern...
3 comments posted 20yrs
posted by simon$actrix.co.nz
3 comments posted 20yrs posted by simon$actrix.co.nz

Starting with LVDS

Dear all I'm starting with LVDS. My task is sending 8-bits signal to LVDS Transmitter port on my board. I declared a 8...
14 comments posted 20yrs
posted by frankschr
14 comments posted 20yrs posted by frankschr

self repairing FPGA s !?

from xilinx data2mem report file START_RSR_TOP (Enables BRAM Redundancy Self-Repair for top half of chip) = off. START_...
0 comments posted 20yrs
posted by antti
0 comments posted 20yrs posted by antti

Third Call for Papers to JCRA 2006

Third Call for Papers =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3...
0 comments posted 20yrs
posted by jcra2006
0 comments posted 20yrs posted by jcra2006

PicoLA: FPGA based logic analyzer

PicoLA is a very simple logic anlazer created by dulse electronics available as free download there http://www.dulseele...
0 comments posted 20yrs
posted by antti
0 comments posted 20yrs posted by antti

post-fit simulation failed

Hello, with the following code snipped I have Problems on synthese/fit process on xst Web/ISE 8.1 (the behavioral simula...
6 comments posted 20yrs
posted by olaf
6 comments posted 20yrs posted by olaf

ISE BaseX customers

I read from the file http://www.xilinx.com/company/press/kits/ise81i/8_1i_faq.pdf the following: --BEGIN-- 14. What hap...
3 comments posted 20yrs
posted by taileb.mehdi
3 comments posted 20yrs posted by taileb.mehdi

FPGA-Programmable power supply

Can I use an FPGA to control a programmable pwer supply..if so are there any such implementations already available..or...
6 comments posted 20yrs
posted by yadurajj
6 comments posted 20yrs posted by yadurajj

Xilinx Partial Reconfiguration add-on module

Xilinx promised for ISE8.1i a "free add-on module for partial reconfiguration". But I still don't see it. Can anybody gi...
4 comments posted 20yrs
posted by taileb.mehdi
4 comments posted 20yrs posted by taileb.mehdi