Field-Programmable Gate Arrays

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Verilog Binary Division

I need a Verilog behavioral model (verilog behavioral code) for: - unsigned 8-bit division The module I have to use is...
15 comments posted 12yrs
posted by kristo.godari
15 comments posted 12yrs posted by kristo.godari

FREE download of HercuLeS high-level synthesis!

Dear all, HercuLeS by Ajax Compilers, Inc. (http://www.ajaxcompilers.com) is an easy to use high-level synthesis (HLS)...
3 comments posted 12yrs
posted by nikolaos.kavvadias
3 comments posted 12yrs posted by nikolaos.kavvadias

microsemi technical support

Hi everyone, this might be a stupid question to ask here but I really do not know where else I can post it. I filed 4 t...
4 comments posted 12yrs
posted by alessandro.basili
4 comments posted 12yrs posted by alessandro.basili

Implementation ingnoring custom IP made with HLS

Hello, I am not entirely sure if this an implementation problem or an HLS problem but i will try here first. I have a m...
0 comments posted 12yrs
posted by turin231
0 comments posted 12yrs posted by turin231

Zynq devices, boards and suppliers

I'd like to pick people's brains about aspects of different *suppliers* of Zynq boards. Avnet and Digilent are front-ru...
24 comments posted 12yrs
posted by spamjunk
24 comments posted 12yrs posted by spamjunk

extra reset pin should not be needed..

Do any of the vendors provide a way to use the global reset net, but avoid having to tie it to a pin. In other words: m...
5 comments posted 12yrs
posted by jhallen
5 comments posted 12yrs posted by jhallen

reset strategy FPGA Igloo

Dear all, I fear that I have an issue with reset time propagation all over my design and this may cause unknown initial...
45 comments posted 12yrs
posted by alessandro.basili
45 comments posted 12yrs posted by alessandro.basili

Book recommendation

Hi, I'm new on this group. I'm starting my final year's project and I'm building a "interpolated multi-axis controller"...
11 comments posted 12yrs
posted by prpabst
11 comments posted 12yrs posted by prpabst

Granularity of components for FPGA synthesis?

Hello, I am busy designing a small microprocessor system, which I have partitioned into the data path, the micro-contro...
7 comments posted 12yrs
posted by jurgen.defurne
7 comments posted 12yrs posted by jurgen.defurne

VTR 7.0 Release Announcement

To the FPGA Research Community, We are pleased to announce the release of VTR 7.0. VTR is an open source f ramework for...
0 comments posted 12yrs
posted by jasonkailuu
0 comments posted 12yrs posted by jasonkailuu

Lattice Diamond & tristate

Hello folks! Unrelated to the other recent thread about Diamond and MachXO2, does anyone know how to make Lattice's Dia...
8 comments posted 12yrs
posted by akuktin
8 comments posted 12yrs posted by akuktin

Lattice diamond / MachXO2

I've recently discovered that Lattice MachXO2 is quite a nice family of low-end FPGAs. I like especially the built-in o...
14 comments posted 12yrs
posted by jhallen
14 comments posted 12yrs posted by jhallen

good SDC reference

Hello All, It has been many years since I used the Synopsys Design Constraint (SDC) la nguage to apply timing constrain...
0 comments posted 12yrs
posted by padudle
0 comments posted 12yrs posted by padudle