Verilog module not working,binary division,shifting problem!!

I don't really want to debug this for you, but one thing I noticed is that you're testing for less than zero on A, which is an unsigned

8-bit reg. If you want to test for less than zero, A should be declared as a signed reg. If you really wanted to test for the MSB of A being set, then say "if (A[7])" rather than "if (A < 0)"

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Gabor

Kristo,

First of all please don't post multiple times. (Here and comp.lang.verilog). Stay on the same thread too.

Now, onto the code. There's some fundamental issues. You're idea is fine - you're coding up basic long division like you do with pen and paper. Just a few tripping points.

I suggest changing this to a 'for' loop. Most synthesizers can handle for loops (if you follow certain rules). While loops can cause more trouble.

Verilog Reg are default unsigned - and I suggest you stick with the default for now.

Knowing this, you'll should see holes in your code. This if clause is always false. It will never execute.

This clause too, will never happen.

That's a start. I haven't check the math, but you're moving in the right direction.

Regards,

Mark

Thank you Mark for your Help :) I found my mistake! I was shifting A and Q separately! My A at the begining is 00000000 when i shift it with a bit it gave me 00000000 and i thought that shift was not working. Instead i want to shift AQ! Let's assume A=01011 and Q=10010 i want to shift AQ 1 bit to the left so i can have 10111 00100!

I know how to shift AQ by one bit: AQ={A,Q}; AQ=AQ

You mean like:

{A,Q} = {A,Q}