I am not entirely sure if this an implementation problem or an HLS problem but i will try here first. I have a microblaze system alongside a custom IP that has memory interfaces for I/O made by HLS. Since I begun using the me mory interface in the custom IP the Vivado implementation ingnore the HLS IP completely (synthesis is completed correrctly). When i used to use other interfaces for IP this problem was not present.
The IP is conencted to the AXI bus as such:
The only issue I see is that the address width of the BRAM generator and th e IP is 32 while for the AXI-BRAM controller is 14 bits and some pins are l eft unconnected. But i do not understand why this would make implementation ingnore the custom IP...