Field-Programmable Gate Arrays

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timing closure

Hi everyone, I know the subject is a bit broad, but I'm having issues in achieving timing closure and I'm trying to add...
2 comments posted 12yrs
posted by alessandro.basili
2 comments posted 12yrs posted by alessandro.basili

Legal Issues Reproducing Old CPU

This might not be the best group to ask, but I figured I would start here. I need to duplicate a 35-year-old CPU. Are t...
29 comments posted 12yrs
posted by ditiris
29 comments posted 12yrs posted by ditiris

Altera EP3CLS70U484C8N

Hi, Does anyone know where I can buy EP3CLS70U484C8N from the shelf ? I'm lookin for only 1 pcs. Best regards Adam
1 comments posted 12yrs
posted by gorskiamalpa
1 comments posted 12yrs posted by gorskiamalpa

FPGA temperature measurement

We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To measure actual die temperature, we built a 19-stage...
13 comments posted 12yrs
posted by jlarkin
13 comments posted 12yrs posted by jlarkin

Actel Designer Warning: CMP201: Net drives no load

Hi everyone, I have several ports of my design that are not driving anything and left 'open' on purpose, using the 'ope...
13 comments posted 12yrs
posted by alessandro.basili
13 comments posted 12yrs posted by alessandro.basili

Synthesis and mapping of ALU

Dear all, I have the following ALU code as part of a data path: -- purpose: simple ALU -- type : combinational -- input...
2 comments posted 12yrs
posted by jurgen.defurne
2 comments posted 12yrs posted by jurgen.defurne

Problem in Xilinx xapp1052 DMA PCIE custom flow

Hi, I am using ML505 XC5VLX110t board for PCIe core implementation. To implemen t the xapp1052 DMA design for my Endpoi...
1 comments posted 12yrs
posted by hima.aj
1 comments posted 12yrs posted by hima.aj

Cascaded floating-point reduction?

y1= 1.5f*y0 - x*y0*y0*y0 ...Note that all quantities are in single precision floating point. I can't write this equatio...
10 comments posted 12yrs
posted by saad1024
10 comments posted 12yrs posted by saad1024

[HELP]problem with asynchronous fifo ip

Hi,all, I have some problem and I need help.I am using fifo ip core of spartan 3a.The write clk is 125MHz.I set read en...
6 comments posted 12yrs
posted by 98308
6 comments posted 12yrs posted by 98308

[cross-post] vlib, vmap, vcom, how it all works...

Hi everyone, I'm trying to understand the details of each individual step from my source code to a running a postlayout...
10 comments posted 12yrs
posted by alessandro.basili
10 comments posted 12yrs posted by alessandro.basili

Xilinx Xcell Journal 84--Xilinx Goes UltraScale

Hey folks, my team just published a new issue of Xcell Journal. The issue h as a cover story on UltraScale, which shoul...
0 comments posted 12yrs
posted by mike.santarini
0 comments posted 12yrs posted by mike.santarini

Parallella-16 lowest-cost xilinx zynq kit

The crowdfunded Parallella-16 starter kit from adapteva seems to be the lowest-cost xilinx zynq starter kit at the same...
0 comments posted 13yrs
posted by acd4usenet
0 comments posted 13yrs posted by acd4usenet

NiosII 8.0 make error Windows XP

I am trying to build a simple hello world example using Nios II v8.0 on a w indows Xp machine. I see the following erro...
5 comments posted 13yrs
posted by vivek.menon79
5 comments posted 13yrs posted by vivek.menon79