I have been programming FPGA with VHDL for some years now. I came from high
-speed full-custom and digital standard cell semiconductor design with cade nce and that was 100% schematic capture.
I have two books: FPGA prototyping by VHDL examples, by Pong P. Chu Circuit Design with VHDL, by Volnei A. Pedroni.
Both books gave me a good introduction to the procedure of mapping somethin g structural (schematic, block diagram) into something behavioural (RTL, FS M), and at the same time cover something I knew, real hardware.
Chu is using Xilinx and Pedroni seems agnostic.
Chu has a short tutorial on a Xilinx project to get started with the toolch ain, and Pedroni has tutorials for Xilinx and Altera. I didn't follow any o f these tutorials as I pretty much understood the FPGA tools by previous to ol experience.
You can have a peek into both books at google books.
Pedroni has a lot of examples on how to use types, both working examples an d examples which will not work. That's the section I use most nowadays.
Other than that, Xilinx has some documents on coding style, both for esthet ics and for speed. Google for "xilinx coding guidelines" as they are hidden in obscure places.
The switch from schematic structural thinking to VHDL behavioural thinking sometimes lead to horrible code. The above books helped me through that per iod, specially regarding use of clock enable instead of gated clocks and av oid inferring unwanted latches. Just remember to replace the clk'event and clk='1' with the modern rising_edge(clk) in the textbook examples.
The biggest hurdle was to accept that the synthesizer could do a better job than me and stop being too clever during design.