Hello folks!
Unrelated to the other recent thread about Diamond and MachXO2, does anyone know how to make Lattice's Diamond and MachXO2 synthesizeand use tristate buffers?
Now, I'm not interested in tristates because "tristates" but because I am trying to save up a bit of space by using a bidirectional bus instead of two unidirectional. But for that, I need to alternate writing to the bus and that is what I need tristates for.
Pursuant of this, in my verilog sources, I have declared the relevant ports as bidirectional (inout), used proper constructs for alternating reading and writing (high impedance and all that), but when I try to synthesize the resulting code, Lattice's synthesizer claims an error to the effect "wire such_and_such is constantly being driven from multiple places" and stops. When I try with Synplify Pro, Synplify does synthesize the tristates, but when Diamond translates that to its own format, I get warnings similar to "unknown attribute: origin_instead_of -- ignoring" (I'm typing this from memory). I take that error to mean that the translation program removed the tristates and left me with broken code.