Field-Programmable Gate Arrays

Xilinx System Generator Black Box

A few weeks back I posted about importing a VHDL, actually a Xilinx Core, into a system generator project as a black bo...

0 comments posted 20yrs

posted by cwoodring

0 comments posted 20yrs posted by cwoodring

Xilinx HardMacro "configurable" ?

Hi, I have a hardmacro that's quite small (2 slices) and that have 2 LUTs in them and I'd like to be able to choose the...

8 comments posted 20yrs

posted by com.246tNt

8 comments posted 20yrs posted by com.246tNt

using ISE and GNU tools for Xilinx V2Pro/V4FX PowerPC

a small intro howto http://xilant.com/content/view/37/2/ and direct link to download for MB and PPC Win32 GCC binaries...

0 comments posted 20yrs

posted by antti

0 comments posted 20yrs posted by antti

Xilinx development board

HI, I just want to know is there any Virtex 4 based development board on which i can add a 400 pin microprocessor and a...

4 comments posted 20yrs

posted by vssumesh_asic

4 comments posted 20yrs posted by vssumesh_asic

Find and fix critical paths in gate level netlist by GOF

GOF, Gates On the Fly, GUI tool to do netlist trace and modification(ECO). New Release of GOF V2.097 with features 1. I...

0 comments posted 20yrs

posted by nandigits

0 comments posted 20yrs posted by nandigits

ISE Simulator Price

What is the price for ISE Simulator? There is no mention of it in Xilinx Online Store. How does it compare to ModelSim X...

5 comments posted 20yrs

posted by u1000393

5 comments posted 20yrs posted by u1000393

open position: developing high-level FPGA programming tools

Galois is looking for a talented software/hardware engineer to join us, for a project pushing the state of the art in F...

0 comments posted 20yrs

posted by fjh-mailbox-48

0 comments posted 20yrs posted by fjh-mailbox-48

low level ethernet interface driver

http://www.rawether.net/

0 comments posted 20yrs

posted by sperrin14.spam.not

0 comments posted 20yrs posted by sperrin14.spam.not

equivalent time sampling

I am designing a data aqu system using an fpga and adc sampling at 250MHz I want to use equivalent time sampling to inc...

10 comments posted 20yrs

posted by maxascent

10 comments posted 20yrs posted by maxascent

Xilinx UCF area constraints disappearing

I have a design with an Aurora RocketIO core and in the UCF file I've added the following lines: INST Inst_rio0_top/Ins...

4 comments posted 20yrs

posted by enquiries

4 comments posted 20yrs posted by enquiries

Memory initialization for synthesis in ISE

I am using the Core Generator to create memories. I used the COE file to initialize them and I simulate behaviour. When...

0 comments posted 20yrs

posted by karagiozhs

0 comments posted 20yrs posted by karagiozhs

Poll: what's would your requirments be for ESL (Electronic System Level) flows?

Hi, I do not want to SPAM all FPGA users, so I am posting this here. Xilinx's marketing department would like to have a...

3 comments posted 20yrs

posted by alherrer

3 comments posted 20yrs posted by alherrer

Communication between FPGA and PC with ethernet

Hello I have to make an connection to a FPGA-borad. http://www.celoxica.com/products/rc300/default.asp This board only...

12 comments posted 20yrs

posted by Roggey

12 comments posted 20yrs posted by Roggey

Xilinx Tight packing : Map error, the tools don't get it ...

Hello, I'm trying to pack something into two SLICEs and the tools don't get it ... I get map error. And it should be po...

6 comments posted 20yrs

posted by com.246tNt

6 comments posted 20yrs posted by com.246tNt

Standby current measurement

Good day to all, Does anyone know of any peculiarities concerning the measurement of the standby current of a DDR RAM?...

0 comments posted 20yrs

posted by rover8898

0 comments posted 20yrs posted by rover8898