Xilinx System Generator Black Box

A few weeks back I posted about importing a VHDL, actually a Xilinx Core, into a system generator project as a black box. The help files give explicit instructions under a heading specifically titled "Importing a Xilinx Core into a Simulink Model". Well the issue was about inserting a CE pin into a core wrapper for a core that does not have a CE pin. I kept trying to build the wrapper and every time I brought it into the Simulink model it would show a CE and CLK pin which it should not. After awhile I gave up and put it aside for awhile. The other day I was reading another part of the help documentation about requirements on the VHDL code to import as a black box an saw that the Verilog code must have all ports in lower case letters. My core is in VHDL but I went and changed the added CE pin to use lower case letters and I think I also put the ce pin after the CLK pin in the entity and component declarations. Low and behold the importation to the simulink model did not have the CE and CLK pins showing and the model even ran calling up Modelsim and everything. What a PITA!!!!!!!!!.

Now that my model is running a bit, I still have issues with the rate at which the model is running. The core I am using is a multichannel MAC FIR. The help files show how to use a CE enable block to drive the ND pin of the core. The core was initially designed to run at 100 KHz input rate and by doing a x2 interpolation I expected a 200KHz output rate. To feed the mulitichannel filter I put a TimeDivision multiplexer in front of the filter driven by 4 sine wave blocks. I had to set the sample time of the sine wave blocks to 1/ 25000. To drive the CE enable block I use the output of the input TimeDivision multiplexer as an input. In my Modelsim output I always see the ND pin high when I want it to toggle at the 100 KHz rate. I've tried putting upsamplers and downsamplers on the input to the CE enable block and always get errors about my sample rates not matching the filter input rates or other errors.

Basically I'm a bit confused as you can probably tell about this whole sample time setting in the blocks. I really first thought if I want the filter to be fed at a 100KSa/s rate I should make all my sinewaves at that rate. But then the multichannel time multiplexer was increasing the sample rate of the sinewaves by 4 so I was getting a 400 KSa/ rate input to my filter. Therefore I made the initial sine waves each at 25 KSa/s. When I turn on the format according to sample rate option I see the output of the multiplexer and the output of the CE block are the same color and both those outputs go to the filter. When I look in Modelsim I see the filter doing a x2 interpolation but the rates of the ND and RDY signals are no where near what I expect 100 and 200 KSa/s respectively? Anyone out there playing with this type stuff?

Tks

Chuck

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cwoodring
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