Hi, I do not want to SPAM all FPGA users, so I am posting this here. Xilinx's marketing department would like to have as much feedback on ESL (Electronic System Level) requirements from designers.
Please let me know by next Tuesday, I am meeting Xilinx on Wednesday.
Thanks,
Alfredo, Nortel has the email address to spam _every_ FPGA user? Wow, what spyware do you guys put in those routers of yours? Who'd've thought Canadians would be so tricky. Eh? Cheers, Syms. p.s. Warning. Post may contain sarcasm! ;-) p.p.s. Seriously Alfredo, have you got any good links so I can read more about ESL? It seems to be in its infancy, but sounds interesting.
What do you consider "Electronic System Level" flow to be? It sounds like you're asking for something generic but I'm not familiar with the terminology.
afaik: the defacto ESL flow: Matlab to FPGA:
The usual suspects:
Food for though:
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