Field-Programmable Gate Arrays

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Standby current measurement

Good day to all, Does anyone know of any peculiarities concerning the measurement of the standby current of a DDR RAM?...
0 comments posted 20yrs
posted by rover8898
0 comments posted 20yrs posted by rover8898

sdram modeling

Hi there I am using a Micron verilog behavioaral mdoel for SDRAM MT48LC16M16A2 which is rated for CL=2 and I want to ad...
0 comments posted 20yrs
posted by andyluotto
0 comments posted 20yrs posted by andyluotto

[Handel-C]Interface with C

Hi all. I have to import a text file in my handel-C source code. The content of the file .txt is an integer. To import...
1 comments posted 20yrs
posted by gioeroby
1 comments posted 20yrs posted by gioeroby

VHDL simulation

I have a schematic of a 4bit adder in my CAD program. It has the ability to create a "VHDL schematic netlist". I've bee...
2 comments posted 20yrs
posted by grant
2 comments posted 20yrs posted by grant

Maxim anounce MAX3421E SPI-USB Host/Peri

For those looking at smaller FPGA and USB, this new device has both Host and Peripheral modes, and has a 26MHz SPI link...
4 comments posted 20yrs
posted by no.spam
4 comments posted 20yrs posted by no.spam

opencores.org ?

Anyone know what happened to opencores.org ..? The last trail is 2005-May.
3 comments posted 20yrs
posted by pbdelete
3 comments posted 20yrs posted by pbdelete

WIFI Compact Flash

Has anybody interface a WIFI compact flash with a FPGA? Could provide any tips or information in how you did it. Regards...
2 comments posted 20yrs
posted by eziggurat
2 comments posted 20yrs posted by eziggurat

Need some Advice, please

Hi all, Question : Is my qualifications (see below) enough to find a job to begin with? or i need something more to kno...
7 comments posted 20yrs
posted by benkhalh
7 comments posted 20yrs posted by benkhalh

User masks in HardCopy and HardCopy II

Hi, I have a few questions regarding user masks in Altera's HardCopy and HardCopy II structured ASICs. The HardCopy han...
3 comments posted 20yrs
posted by shyam.thoziyoor
3 comments posted 20yrs posted by shyam.thoziyoor

VHDL or verilog

hi, ive completed a introductory book on vhdl, but not mature enough to do a real world complex designs using vhdl. i'v...
8 comments posted 20yrs
posted by manusha
8 comments posted 20yrs posted by manusha

ISVLSI 2006 - Call for Participation

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + IEEE International Symposium on VLSI 2006 + + +...
0 comments posted 20yrs
posted by isvlsi06
0 comments posted 20yrs posted by isvlsi06

DDR SDRAM Controller

Hi there, unfortunately I have problems with DDR SDRAM Controller. I have an Avne board with Xilinx Virtex-II FPGA (xc2...
35 comments posted 20yrs
posted by annedorianashley
35 comments posted 20yrs posted by annedorianashley

pci express ac coupling

Hi all Does anyone know whether the ac coupling caps for PCIExpress should be located at the gold fingers or at the bri...
2 comments posted 20yrs
posted by colin_toogood
2 comments posted 20yrs posted by colin_toogood