Parameterized Comparator Verilog Code

Feb 20, 2006 1 Replies

Hello:



I am trying to write some code for a comparator. Is it possible to write the code as so



module comparator(A_lt_B, A_gt_B, A_eq_zero, B_eq_zero, A, B);



parameter D_Width = 32; output A_lt_B, A_gt_B, A_eq_zero, B_eq_zero; reg A_lt_B, A_gt_B, A_eq_zero, B_eq_zero; input [D_Width-1:0] A; input [D_Width-1:0] B;



always@(A or B) begin if(A>B) A_gt_B = 1; else if (A


1) you don't have statements for results of false. 2) you can have AB);

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