Hi All,
I am trying to infer a adder with a carry in and carry out in Xilinx ISE 7.1. For the unsigned adder case it is inferred properly, i.e carry in is fed to the slice adding the LS bits and Carry out taken from the COUT line of the slice adding the MS bits. However when I generate a signed adder (by sign extension) the above does not happen. The carry in is properly created, but the carry out is not taken as the output of the COUT signal of the slice where the MS bits are added. Instead another LUT is used to add the MS bits (again) and the cout from prev stage and then this is used as the carry out. Why the difference? Below is the VHDL I am using to generate the adder
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-- Generic Adder with Carry In and Carry Out
--------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;
entity GenAdder is generic( gDATA_I_WIDTH: natural := 16; -- data input width gSIGNED: boolean := true -- signed adder? ); port( A: in std_logic_vector(gDATA_I_WIDTH-1 downto 0); B: in std_logic_vector(gDATA_I_WIDTH-1 downto 0); Cin: in std_logic; S: out std_logic_vector(gDATA_I_WIDTH-1 downto 0); Cout: out std_logic ); end entity GenAdder;
architecture rtl of GenAdder is
signal sum: std_logic_vector(gDATA_I_WIDTH downto 0); signal A_ex,B_ex: std_logic_vector(gDATA_I_WIDTH downto 0);
begin
---------------- -- signed adder ---------------- gensigned: if gSIGNED generate A_ex