multiphase data extraction question

Because you are simulating without timing.

The problem will be meeting the the setup time to the flipflop clocked by phase 0, sourced by the flip flop clocked by phase 270. You will only have .25 of a cycle, and depending on the clock frequency and the routing delays, the setup time will not be met.

In your circuit, the first path has 1 cycle available, the second path has .75 of a cycle, the third path has .5 of a cycle, and the fourth path has .25 of a cycle. In Xilinx's circuit, no path has less than .75 of a cycle.

Cheers, Philip Freidin

Philip Freidin Fliptronics

Philip,

Then if i use strongs timing constraints and the constraints are satisfied implementing my circuit, it should works ? I have well understood ?

thanks a lot Sandro

Yep, I agree with Philip. Just to add, if the OP can meet the timing because (say) the clock frequency is low enough, they'd probably be able to have a better design by dumping the DCM phase shift idea, using the DCM to multiply the clock by four and then using that clock to sample the data instead. Cheers, Syms.

Symon,

I agree with you... maybe if the frequency is low enough (so that my circuit will works...) probably I don't need the multiphase data extraction...

thanks Sandro

We have an application where we need 4 phase sampling of a differential (LVPECL) input. I think we found a way to use the IDDRs from the IOBs associated with both + and - differential pads on V4 devices to accomplish this. The FPGA editor seems to show a path from the positive pad to the inverting input of the negative pad's IBUFDS. Therefore the IDDR in the negative pad's IOB can be used, but the data is inverted (we can deal with that downstream). We coded up the following rtl instantiating the IBUFDSs and IDDRs, and it runs all the way through P&R with no errors, so long as you don't put a loc constraint on the negative pad (?).

buf0 : ibufds port map ( i => data_p, ib => data_n, o => data_async(0));

buf1 : ibufds port map ( i => data_n, -- reversed polarity ib => data_p, -- reversed polarity o => data_async(1)); -- inverted

ddr0 : iddr generic map ( ddr_clk_edge => "SAME_EDGE_PIPELINED", init_q1 => '0', init_q2 => '0', srtype => "sync") port map( q1 => data(0), q2 => data(2), c => clk(0), ce => vcc, d => data_async(0), r => reset, s => gnd);

ddr1 : iddr generic map ( ddr_clk_edge => "SAME_EDGE_PIPELINED", init_q1 => '0', init_q2 => '0', srtype => "sync") port map( q1 => data(1), -- inverted q2 => data(3), -- inverted c => clk(1), ce => vcc, d => data_async(1), -- inverted r => reset, s => gnd);

Q: Has anybody else tried this? The documentation does not say anything about this secondary input path. We sent a test case to our local FAE, but have not heard back yet. It certainly seems to work as far as the tools go, but we don't have a good way to check it out physically on a board yet.

Thanks,

Andy Jones

Andy, Neat solution!! You might like to check out Brian's post entitled "DIFF_OUT buffer example". Cheers, Syms.