Field-Programmable Gate Arrays

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Microblaze on Spartan3

Hi Guys Does anyone have a CLB / LUT/ FF/ BRAM count for the microblaze with and without the FPU on a Spartan 3 ? I'm tr...
2 comments posted 20yrs
posted by noelhurley
2 comments posted 20yrs posted by noelhurley

Anyone with Insight DS-V2LC Board Rev. 2 datasheet?

Hello everybody: I was given this board but I can not find the datasheet of it. It has a Virtex II device (XC2V1000FG25...
5 comments posted 20yrs
posted by frank.invalid
5 comments posted 20yrs posted by frank.invalid

DDR2 FPGA PWB SIMULATION

Greetings, We are doing a design that uses an Altera Cyclone II to drive three DDR2 memory chips. Looking at reference...
0 comments posted 20yrs
posted by nospam
0 comments posted 20yrs posted by nospam

floating point MAC, duh!

[ranton] Considering the vast improvements in DSP-type IP and chip resources, I'm baffled as to why multiply-accumulate...
0 comments posted 20yrs
posted by brannonking
0 comments posted 20yrs posted by brannonking

FPGA communication, I2C and DAC

I would like to use an FPGA for a motor control application. I have worked with FPGAs before and am comfortable with wh...
7 comments posted 20yrs
posted by jim.bogdanowicz
7 comments posted 20yrs posted by jim.bogdanowicz

XUP Vertex II J5 Expansionheader Voltage

Hello, on the "Digilent XUP Vertex-II" the J5 and J6 connectors (Low Speed Extension Connectors) run with 2.5V, althoug...
1 comments posted 20yrs
posted by llenz
1 comments posted 20yrs posted by llenz

PPC Linux SoC on Virtex4 in 4 hours !?

Setting up MicroBlaze-uClinux on new FPGA board is a matter of hours - with PPC linux, well there are gurus around clai...
11 comments posted 20yrs
posted by Antti.Lukats
11 comments posted 20yrs posted by Antti.Lukats

conv_integer

Hallo, how much clock cycles takes a conv_integer operation? Many Thanks Marco
4 comments posted 20yrs
posted by marc
4 comments posted 20yrs posted by marc

32 bit select map

Anyone tried to use 32 bit select map programming for virtex4 chips? If you did let me know what clock speed you were ab...
0 comments posted 20yrs
posted by pilwoochun
0 comments posted 20yrs posted by pilwoochun

Xilinx MIG

Hi I am trying to design a DDR memory interface using Xilinx MIG 007 rel 6 However it is only generating two files - a...
3 comments posted 20yrs
posted by maxascent
3 comments posted 20yrs posted by maxascent

How do I make dual-port RAM from single port RAM?

Hi, there: In my application, a RAM needs to be written/read from two sets of data/address ports simultaneously. Howeve...
34 comments posted 20yrs
posted by Frank
34 comments posted 20yrs posted by Frank

New XC9572 decoupling newbie question :-)

Hey ! Cool everything fit into my XC9572 and work like a charm :-) Now should I used some decoupling for the xc9572, I/O...
4 comments posted 20yrs
posted by a
4 comments posted 20yrs posted by a

Observed a bug in the Model sim V 6.0a

Hi all, I did observed a problem in the model sim. I was simulating a code similar to the one given below. module a (in...
0 comments posted 20yrs
posted by vssumesh_asic
0 comments posted 20yrs posted by vssumesh_asic