Hi all, I did observed a problem in the model sim. I was simulating a code similar to the one given below.
module a (input a, output b); wire local_variable c; assign c = a; tasks ..... .......... always @(*) begin .......... .......... end endmodule
But the assignment c=a is not working some times. It always works if i declare it as a reg and include it in the always block. But this will not work if i use it part of the assign statement. the intresting part of it is that it will not work in the first pass. At the second time the execution enters the loops it simply executes. I can sidestep the problem by declaring it as a reg but i want to know the reason. Did any of you observed similar problems. Is this due to any knid of bug in the modelsim. regards Sumesh V S