Hi Folks,
Both Precision Synthesis and Altera Quartus 2.0 cannot infer flops with async reset and enable in the following code. I have checked that the nclk and nrst_n are properly connected to the module.
What am I missing?
TIA, Sanjay
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reg [23:0] irq_event_reg [0:1];
always@(posedge nclk or negedge nrst_n) begin : irq_event_reg_sync if(!nrst_n) begin irq_event_reg[0]