Hi Folks,
Both Precision Synthesis and Altera Quartus 2.0 cannot infer flops with async reset and enable in the following code. I have checked that the nclk and nrst_n are properly connected to the module.
What am I missing?
TIA, Sanjay
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reg [23:0] irq_event_reg [0:1];
always@(posedge nclk or negedge nrst_n) begin : irq_event_reg_sync if(!nrst_n) begin irq_event_reg[0]
Sorry, In this particular case, the sync enable is not present. I forgot to notice that I had edited that part as a test. In anycase, enable or no enable, the synthesizer complains that it cannot infer a flop.
-sanjay
Just a guess, but what if you make two regs rather than a reg array (memory) with two elements. It's isn't uncommon for compilers to treat arrays only as a unit and not as individual elements, even when the elements are always referenced by constant subscripts.
Hope this helps,
-Chris
***************************************************************************** Chris Clark Internet : snipped-for-privacy@world.std.com Compiler Resources, Inc. Web Site :------------------------------------------------------------------------------
Looks like your theory is correct Chris. Thanks.
-sanjay
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