As someone else suggested, you could time-multiplex the two ports, which will take a double-speed clock and extra logic for the multiplexing. And this assumes that you are treating this as a synchronous RAM.
And someone else suggested that you look at your application and see whether you really need a full dual-port RAM, or whether you are dealing with a special case where you can segregate it into independent parts.
You could build the memory from multiple smaller RAMs and add decode logic to allow you to do two writes, as long as the writes were to separate RAMs. If they weren't, one of them would have to wait until the next cycle. This requires that the other logic trying to do the write be able to wait if the memory was "busy". Note that real dual-port memories are effectively implemented this way, except that the RAM granularity is a single word in the memory. The designers of those have the advantage that they are designing all the decode logic, down to the word level.
You can reduce the chance of collisions in this scheme by choosing which address bits select a RAM and which ones select a word in the RAM, if you know something about the likely access patterns. For example, it may be more likely that two memory writes are going to the same half of the memory than that they are both going to even (or odd) addresses.
If you can't multiplex, and can't deal with collisions, then you are out of luck. If you want to use predefined RAMs with their predefined single-port decoding logic, then you are stuck. Getting true dual-port requires specialized decode logic in the RAM.