How do I make dual-port RAM from single port RAM?

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Hi, there:

In my application, a RAM needs to be written/read from two sets of
data/address ports
simultaneously. However, in the ASIC library I can only instantiate some
single port RAM
and RAM which can be written in one port and read from the other port.

How shall I solve this problem?

Thank you.




Re: How do I make dual-port RAM from single port RAM?
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estimate your worst case data rates and take a ram with
the sum of these data-rates (plus overhead) ...

then you need to build some logic to switch between
Port A and B to transfer concurrent access to a
sequential access scheme


bye,
Michael

Re: How do I make dual-port RAM from single port RAM?
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Michael SchF6%berl wrote:
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Re: How do I make dual-port RAM from single port RAM?
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You might get a better idea of the particulars by looking at a data
sheet for IDT dual-port memories.  (www.idt.com)

Re: How do I make dual-port RAM from single port RAM?
Senior Library Design Engineer  (NEW)    The candidate should possess a
BSEE degree (MSEE preferred) with emphasis in VLSI circuit design.  
    5+ years industrial experience designing CMOS VLSI standard cell
libraries.  
    Full understanding of the ASIC design flow and  the role of standard
cell libraries.  
    Experienced in full custom design and layout.
    Knowledge of the cell characterization process.  
    Basic understanding of silicon processing technology.
    Understanding of place and route tools, and how they work.
    Comfortable with the Linix operating system and strong programming
skills in perl.  
    Experience working with silicon foundries, preferably TSMC.
    Full understanding of the following IC Design tools:
            HSPICE
            Verilog logic simulation
            Cadence Composer
            Cadence Virtuoso
            Synopsys Design Compiler
    A proven track record of successful design projects - completed on
schedule.
    Excellent communication skills.
    Leadership skills and a personal commitment to the team's success are
also required attributes
Junior Library Design Engineer (NEW)     The candidate should possess a
BSEE degree (MSEE preferred) with emphasis in VLSI circuit design.  
    3+ years industrial experience designing CMOS digital circuits.  
    Understanding of circuit simulation with SPICE.
    Experienced with physical design rules and IC layout.
    Knowledge of the Cadence design tools.
    Some experience with Verilog modeling and synthesis tools.
    Good computer skills and moderate programming experience with perl.
    Strong team member with positive learning attitude.
    Good oral and written communication skills.
What we expect from you:
If you find this opening interesting then kindly forward your profile
in word format along with your current CTC & expected CTC details to
snipped-for-privacy@priorityoneindia.com ASAP. Kindly inform the same to your
colleagues and friends.



Thanks & Regards,

Komal Tripathi.

____________________________

PriorityONE Consulting

Your Success is our PRIORITY # 1!

Contact me:

India Mobile: +91-9945341452.

Direct Lines: 080-41313872

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John_H wrote:
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Re: How do I make dual-port RAM from single port RAM?
For some applications 2 Srams can be used in an alternate buffer
configuration. I assume your 2 ports have similar issue rates otherwise
you may have to mux in time.


Re: How do I make dual-port RAM from single port RAM?
Frank, you posted this in the FPGA newsgroup.
In FPGAs, most RAM structures are naturally dual-ported, e.g. the
Virtex BlockRAMs.
You get two ports, whether you asked for it or not!
Peter Alfke, Xilinx Applications.

Frank @ CN wrote:
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Re: How do I make dual-port RAM from single port RAM?

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Yeah, the original codes are designed with Xilinx DPRAM with a functional
testbenches,
now I need to convert the codes into ASIC implementation. The tougher part
of it is, I
have little understanding of the functionality of the design.



Re: How do I make dual-port RAM from single port RAM?
For dual read ports and a single write port, this is easy.  You just
use two RAMs and always write to both of them together, but read from
them separately, with each treated as a separate read port.  For dual
write ports, it gets a lot harder.


Re: How do I make dual-port RAM from single port RAM?

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Yeah, there are RAMs in the ASIC library supporting dual read/single write.
I need to make dual read/write out of it. How can I do it now?

Thanks.



Re: How do I make dual-port RAM from single port RAM?
As someone else suggested, you could time-multiplex the two ports,
which will take a double-speed clock and extra logic for the
multiplexing.  And this assumes that you are treating this as a
synchronous RAM.

And someone else suggested that you look at your application and see
whether you really need a full dual-port RAM, or whether you are
dealing with a special case where you can segregate it into independent
parts.

You could build the memory from multiple smaller RAMs and add decode
logic to allow you to do two writes, as long as the writes were to
separate RAMs.  If they weren't, one of them would have to wait until
the next cycle.  This requires that the other logic trying to do the
write be able to wait if the memory was "busy".  Note that real
dual-port memories are effectively implemented this way, except that
the RAM granularity is a single word in the memory.  The designers of
those have the advantage that they are designing all the decode logic,
down to the word level.

You can reduce the chance of collisions in this scheme by choosing
which address bits select a RAM and which ones select a word in the
RAM, if you know something about the likely access patterns.  For
example, it may be more likely that two memory writes are going to the
same half of the memory than that they are both going to even (or odd)
addresses.

If you can't multiplex, and can't deal with collisions, then you are
out of luck.  If you want to use predefined RAMs with their predefined
single-port decoding logic, then you are stuck.  Getting true dual-port
requires specialized decode logic in the RAM.


Re: How do I make dual-port RAM from single port RAM?
Sounds like a powerful FPGA argument:
Ifyou really need a true dual-port memory (read and write from either
or both ports simultaneously), you are out-of-luck in the ASIC world,
but you can do this just fine in FPGAs.
Nice to know we have such an edge...
Peter Alfke, Xilinx


Re: How do I make dual-port RAM from single port RAM?
Presumably this depends on what ASIC libraries you have.  There is no
inherent reason that an ASIC library could not include dual-port
memories.  Apparently the original poster's didn't.


Re: How do I make dual-port RAM from single port RAM?

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True, some TSMC ASIC libraries had dual-read/write memories, and they used
to provide
memory generators which enables creating the memory blocks of any capacity.

After we changed foundry, things got really complicated. In the new library,
only a few memories
are provided and the width & depth are also fixed. It becomes very
inefficient to use these RAMs.

I guess I am out of luck on memory issues this time.




Re: How do I make dual-port RAM from single port RAM?
Quoted text here. Click to load it

That is completely dependent on the ASIC libraries. In FPGA you are out of
luck with higer amount of ports that are available in some ASIC libraries.
For example in the ASIC library I use there are: single port, 1 read 1 write,
dual port and 4-port memories. And then different versions of those
(density, power, speed).

--Kim

Re: How do I make dual-port RAM from single port RAM?
Senior Library Design Engineer  (NEW)    The candidate should possess a
BSEE degree (MSEE preferred) with emphasis in VLSI circuit design.  
    5+ years industrial experience designing CMOS VLSI standard cell
libraries.  
    Full understanding of the ASIC design flow and  the role of standard
cell libraries.  
    Experienced in full custom design and layout.
    Knowledge of the cell characterization process.  
    Basic understanding of silicon processing technology.
    Understanding of place and route tools, and how they work.
    Comfortable with the Linix operating system and strong programming
skills in perl.  
    Experience working with silicon foundries, preferably TSMC.
    Full understanding of the following IC Design tools:
            HSPICE
            Verilog logic simulation
            Cadence Composer
            Cadence Virtuoso
            Synopsys Design Compiler
    A proven track record of successful design projects - completed on
schedule.
    Excellent communication skills.
    Leadership skills and a personal commitment to the team's success are
also required attributes
Junior Library Design Engineer (NEW)     The candidate should possess a
BSEE degree (MSEE preferred) with emphasis in VLSI circuit design.  
    3+ years industrial experience designing CMOS digital circuits.  
    Understanding of circuit simulation with SPICE.
    Experienced with physical design rules and IC layout.
    Knowledge of the Cadence design tools.
    Some experience with Verilog modeling and synthesis tools.
    Good computer skills and moderate programming experience with perl.
    Strong team member with positive learning attitude.
    Good oral and written communication skills.
What we expect from you:
If you find this opening interesting then kindly forward your profile
in word format along with your current CTC & expected CTC details to
snipped-for-privacy@priorityoneindia.com ASAP. Kindly inform the same to your
colleagues and friends.



Thanks & Regards,

Komal Tripathi.

____________________________

PriorityONE Consulting

Your Success is our PRIORITY # 1!

Contact me:

India Mobile: +91-9945341452.

Direct Lines: 080-41313872

E-mail: snipped-for-privacy@priorityoneindia.com



PriorityONE Consulting provides the best technical talent to suit the
needs of

high end software companies  for the entire technology and hierarchy
spectrum.

We serve our clients and our candidates with respect and commitment.


Re: How do I make dual-port RAM from single port RAM?

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You can instantiate FOUR rams and implement a valid bit for each location in
a register.
PortA can write to RAM0,RAM1 and read from RAM0 and RAM2
PortB can write to RAM2,RAM3 and read from RAM1 and RAM3

When PortA writes to address position 17, both RAM0[17] and RAM1[17] are
updated and the
VALID_BIT[17] is set to 0 indicating that RAM0,1 are valid instead of
RAM2,3.

When PortB reads address position 17, both RAM1 and RAM3 are read.
A multiplexer on the output is controlled by the selected VALID_BIT,
and since VALID_BIT[17] is zero, it will select the output of RAM1 over
RAM3.

Obviously this is going to use some gates,so it is not practical for large
SRAMs.
Running the RAM at 2 x frequency is going to cost a lot less.




--
Best Regards,
Ulf Samuelsson
We've slightly trimmed the long signature. Click to see the full one.
Re: How do I make dual-port RAM from single port RAM?
That is a clever solution that I hadn't thought of.  Of course, your
VALID_BIT array needs the capabilities of a true dual-port memory.  So
this doesn't really build a dual-port memory just out of RAMs.  It
builds it from 4 RAMs and a smaller dual-port memory (just as many
elements, but only 1 bit wide).  You would have to build that smaller
dual-port memory out of flip-flops.  The result still might be smaller
than building the full-size memory out of flip-flops.


Re: How do I make dual-port RAM from single port RAM?

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Morning Samuelsson & sharp, I haven't got time to study the sequence of the
clever
solution yet. I want to know is, does it have the function of a full dual
port R/W RAM
if the R/W accesses of both ports are random? My RAM is 130*6bit, and the IP
uses
eight pieces of this RAM.

TIA




Re: How do I make dual-port RAM from single port RAM?
Yes, Ulf's solution gives full dual-port functionality for arbitrary
addresses (though of course you have to decide which port gets the last
word in case of simultaneous writes to the same address, as with any
dual-port memory).

But with your small word size of 6 bits, this may not be
cost-effective.  The VALID_BIT array requires similar logic to a
1-bit-wide dual-port memory (not quite the same, since port 0 always
writes a value of 0 and port 1 always writes a value of 1).  So you
have to design something close to a 130*1bit dual-port memory out of
flip-flops and logic, and use that with four 130*6bit RAMs (or two
130*6bit dual-read/single-write RAMs, since you indicated you have
those).  You might be as well off to design a 130*6bit dual-port memory
from flip-flops and logic.


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