Field-Programmable Gate Arrays

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PCI configuration for ML310

Hello All, I'm trying to get Linux working on the Xilinx ML310 using a PCI hardware configuration, other than the one p...
5 comments posted 20yrs
posted by igelado
5 comments posted 20yrs posted by igelado

VirtexII routing data widths

This might be a dumb question, but I can't seem to find it in the Xilinx documentation anywhere. I'm using a VirtexII (...
11 comments posted 20yrs
posted by chris_frankiNO
11 comments posted 20yrs posted by chris_frankiNO

Virtex-4 RAMB16 relative placement

XST is synthesising the following verilog code to a 8192x24-bit RAM. module bram_8k (clk, addr, di, do); input clk; inp...
1 comments posted 20yrs
posted by ksudheerkumar
1 comments posted 20yrs posted by ksudheerkumar

Serious problem with XST

Hi, I encounter a serious problem with xst when I try to synthesize a design. The design consists of several components...
5 comments posted 20yrs
posted by alles
5 comments posted 20yrs posted by alles

FPGA: Model-SIm XE problem

Hi I have made a generic component like below entity fifo is generic( AW : integer; PROG_EMPTY_THD : std_logic_vector(A...
4 comments posted 20yrs
posted by
4 comments posted 20yrs posted by

tricks to make large PLAs fast?

I have a design with a large PLA, and I'm trying to make it run fast in a Spartan-3. It's too big for block RAM, since...
20 comments posted 20yrs
posted by eric
20 comments posted 20yrs posted by eric

miniuart

hello i plan on synthesizing miniuart (opencores.org) onto a spartan 3 demo board. but then i dont know how to test it....
10 comments posted 20yrs
posted by zhangweidai
10 comments posted 20yrs posted by zhangweidai

Coregen ISE 6.1

Hello, after starting Coregen 6.1i, no IP core is sohwn although I have done Get models under the Tools button. Do I ha...
1 comments posted 20yrs
posted by foag
1 comments posted 20yrs posted by foag

ERROR:MapLib:482

Hi I 'm a student working with XPS 7.1 and I get this error ERROR:MapLib:482 - Blockram ramb16_s9_s9_0 is a memory mapp...
5 comments posted 20yrs
posted by michiel.vanderlinden
5 comments posted 20yrs posted by michiel.vanderlinden

VGA specification

Hi all, Does any of you knows where can I obtain the VGA specification (I believes it is IBM's) ? Thanks in advance, Mor...
8 comments posted 20yrs
posted by me_2003
8 comments posted 20yrs posted by me_2003

Virtex 4 Multiplier RPM Constraints?

Hi, I am trying to create a Xilinx Core Generator multiplier for Virtex 4 with RPM constraints. However, neither ISE 7....
5 comments posted 20yrs
posted by lovesinghal
5 comments posted 20yrs posted by lovesinghal

about Xilinx Chipscope

Hi, everyone. I want to do a presentation about the introduction about Xilinx Chipscope on the meeting of my lab. Since...
2 comments posted 20yrs
posted by yyqonline
2 comments posted 20yrs posted by yyqonline

FIFO design

what is the difference in using DPRAM instead of RAM for asynchronous FIFO design? Is it necessary to use DPRAM for desi...
1 comments posted 20yrs
posted by siva007i
1 comments posted 20yrs posted by siva007i

XC9500 JTAG Initialize problem

Hai XC9500 is not initialized and .log file directing me to look for hardwar config problems. I have Connected Parallel...
3 comments posted 20yrs
posted by scpadala
3 comments posted 20yrs posted by scpadala

fpga to 5v ttl logic

what shall I use to convert FPGA i/o pins to 5v TTL compatible levels? 50 i/o pins, tri-state, TTL R
33 comments posted 20yrs
posted by aiiadict
33 comments posted 20yrs posted by aiiadict