Hi
I am trying to design a DDR memory interface using Xilinx MIG 007 rel 6 However it is only generating two files - a vhdl file containing a packag and a ucf file. Using a Virtex device a lot more files are created. Is thi a bug or am I using it wrong?
Thanks
Jon
XAPP709 states that a 200-MHz DDR SDRAM can be built using MIG coregen, however, when I run mig006_rel6 ISE7.1.04, I don't see V4s on the drop down selector. What's the story?
Brad
mig007_rel6 is not "MIG coregen".
The MIG you're looking for is included in CORE Generator, it's not a standalone tool. You can install it via the online updates function in CORE Generator. Last time I checked there was MIG available for ISE8.1, so this only works for the CORE Generator included in ISE7.1.
cu, Sean
Just checked again: There now is MIG 1.5 for ISE8.1 available.
cu, Sean
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