Field-Programmable Gate Arrays

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Shift Register synthesis??

Hi, while i was synthesizing a simple shift register i got an odd behavior. The device i'm using is a virtex2pro (xc2vp...
4 comments posted 20yrs
posted by giovannibusonera
4 comments posted 20yrs posted by giovannibusonera

problem

Hi, I learn VHDL. I got text: " Compiling 'komp.vhd' in 'H:\PROGRAMY\WARP\BIN'. VHDL parser (h:\programy\warp\bin\vhdlf...
3 comments posted 20yrs
posted by spawnek
3 comments posted 20yrs posted by spawnek

EDK remote TCP debug

Hi, I'm trying to debug an application. I downloaded the .elf file to the board, and then started XMD. I followed the i...
2 comments posted 20yrs
posted by dasani8888
2 comments posted 20yrs posted by dasani8888

Parallel readback on Spartan IIE

Hi All, Having a few problems implementing readback on a Xilinx SpartanIIE device. We have a uP programming via the par...
2 comments posted 20yrs
posted by map.nospam
2 comments posted 20yrs posted by map.nospam

Connect USB device to Spartan 3 FPGA

I am new to FPGA's and its programming language VHDL. I am working on an Computer Science senior project and have a few...
1 comments posted 20yrs
posted by AaronDBenson
1 comments posted 20yrs posted by AaronDBenson

XST synthesis gripe/sub-optimization

I've been bitten several times by XST producing sub-optimal results by trying to use the flip-flop enable when it doesn...
1 comments posted 20yrs
posted by johnp3+nospam
1 comments posted 20yrs posted by johnp3+nospam

can bus protocol on fpga

Hello, I would like to implement a can bus protocol on a fpga, in a way to link a pc and a can bus via a pci fpga I/O ca...
8 comments posted 20yrs
posted by adrien.bureau
8 comments posted 20yrs posted by adrien.bureau

V4 LVDS_25 IBIS models

I tried examining the V4 LVDS input IBIS models last night. Loading them into Edality's free IBIS viewer gave me the fo...
0 comments posted 20yrs
posted by brimdavis
0 comments posted 20yrs posted by brimdavis

VHDL

Now, I used the state machine to apply to VHDL. In my case, there are two states, S0 and S1. When I press a button, S0...
6 comments posted 20yrs
posted by laura_pretty05
6 comments posted 20yrs posted by laura_pretty05

5v Xilinx development board

Does anybody know where I can get hold of a cheap Xilinx development board that has an FPGA with 5v I/O?
8 comments posted 20yrs
posted by g_pearman
8 comments posted 20yrs posted by g_pearman

FPGA imple. of aes

We have been doing a project on high speed aes using subpippelining concepts we would be happy if we find some code whic...
23 comments posted 20yrs
posted by manjunath.rg
23 comments posted 20yrs posted by manjunath.rg

DCM question

Hi, for my project I'd like to use the same 25MHz clock signal (coming from an external oscillator) for both the DSP an...
8 comments posted 20yrs
posted by marco
8 comments posted 20yrs posted by marco

Crosstalk Analysis on a FPGA

How exactly is crosstalk analysis performed on a FPGA (in particular Xilinx Virtex series). Are there particular tools...
1 comments posted 20yrs
posted by moneyk
1 comments posted 20yrs posted by moneyk